Ad hoc wireless multi-hop networks (AHWMNs) are communication networks that consist entirely of wireless nodes, placed together in an ad hoc manner, i.e. with minimal prior planning. All nodes have routing capabilities, and forward data packets for other nodes in multi-hop fashion. Nodes can enter or leave the network at any time, and may be mobile, so that the network topology continuously experiences alterations during deployment. AHWMNs pose substantially different challenges to networking protocols than more traditional wired networks. These challenges arise from the dynamic and unplanned nature of these networks, from the inherent unreliability of wireless communication, from the limited resources available in terms of bandwidth, processing capacity, etc., and from the possibly large scale of these networks. Due to these different challenges, new algorithms are needed at all layers of the network protocol stack. We investigate the issue of adaptive routing in AHWMNs, using ideas from artificial intelligence (AI). Our main source of inspiration is the field of Ant Colony Optimization (ACO). This is a branch of AI that takes its inspiration from the behavior of ants in nature. ACO has been applied to a wide range of different problems, often giving state-of-the-art results. The application of ACO to the problem of routing in AHWMNs is interesting because ACO algorithms tend to provide properties such as adaptivity and robustness, which are needed to deal with the challenges present in AHWMNs. On the other hand, the field of AHWMNs forms an interesting new application domain in which the ideas of ACO can be tested and improved. In particular, we investigate the combination of ACO mechanisms with other techniques from AI to get a powerful algorithm for the problem at hand. We present the AntHocNet routing algorithm, which combines ideas from ACO routing with techniques from dynamic programming and other mechanisms taken from more traditional routing algorithms. The algorithm has a hybrid architecture, combining both reactive and proactive mechanisms. Through a series of simulation tests, we show that for a wide range of different environments and performance metrics, AntHocNet can outperform important reference algorithms in the research area. We provide an extensive investigation of the internal working of the algorithm, and we also carry out a detailed simulation study in a realistic urban environment. Finally, we discuss the implementation of ACO routing algorithms in a real world testbed.

https://doc.rero.ch/record/9027/files/2007INFO001.pdf

Adaptive routing in ad hoc wireless multi-hop networks

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

https://downloads.hindawi.com/journals/jece/2012/509465.pdf

Networks on chips: structure and design methodologies

Switching of a single plasmon interacting with n equally spaced quantum dots coupled to one-dimensional surface plasmonic waveguide is investigated theoretically via the real-space approach. We showed that the transmission and reflection of a single plasmon can be switched on or off by dynamically tuning and changing the number of the equal transition frequencies of the quantum dots. Increasing the number of doped quantum dots having the equal transition frequencies results in the wide–band reflection of a single plasmon and the complete transmission peaks near the resonant frequencies.

Single Plasmon Switching with n Quantum Dots System Coupled to One-Dimensional Waveguide

Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region.

A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region

Switching of a single plasmon interacting with equally spaced quantum dots coupled to one-dimensional surface plasmonic waveguide is investigated theoretically via the real-space approach. We showed that the transmission and reflection of a single plasmon can be switched on or off by dynamically tuning and changing the number of the equal transition frequencies of the quantum dots.

Single Plasmon Switching with n Quantum Dots System Coupled to One-Dimentional Waveguide

In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

Process variation study of Ground Plane SOI MOSFET

An all-optical switch composed of two interacting nanoparticles in front of an optical dielectric slab waveguide is proposed An incident optical signal is coupled to the optical waveguide after scattering by the two nanoparticles The scattered fields interfere constructively or destructively depending on the degree of optical transparency the nanoparticles induced by an optical control signal The considered nanoparticles have a metallic core coated by an outer shell with three-level clusters such that the nanoparticles can exhibit electromagnetically induced transparency A dipole-approximation model-based analysis reveals that a high rejection ratio can be achieved using the proposed configuration

Nanoscale all-optical plasmonic switching using electromagnetically induced transparency

In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of the scheme, the proposed algorithm was compared to the XY, Odd-Even, and DyAD routing models. The simulation results show that in realistic (Transpose) traffic as well as in heavy packet traffic, the proposed model has less average delay and peak power compared to the other routing models. In addition, the maximum temperature in the proposed algorithm is less than those of the other routing algorithms.

Ant colony based routing architecture for minimizing hot spots in NOCs

In this paper, a low-power architecture (ByZFAD Stands for Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications include the removal of the shift of B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of the binary counter, and removal of the partial product shift. To show the efficiency of the architecture, we have compared the switching activity of the proposed architecture with that of the conventional architecture for a radix-2 shift-and-add multiplier. The results for a 32-bit multiplier show that, the proposed architecture lowers the total switching activity up to 76% when compared to the traditional architecture.

Ali Afzali Kusha

Papers

Process variation study of Ground Plane SOI MOSFET

Nanoscale all-optical plasmonic switching using electromagnetically induced transparency

Ant colony based routing architecture for minimizing hot spots in NOCs

ByZFAD: a low switching activity architecture for shift-and-add multipliers