A
Ali Shafiee
Researcher at University of Utah
Publications - 19
Citations - 2265
Ali Shafiee is an academic researcher from University of Utah. The author has contributed to research in topics: Interleaved memory & Memory controller. The author has an hindex of 11, co-authored 19 publications receiving 1565 citations. Previous affiliations of Ali Shafiee include Sharif University of Technology.
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Journal ArticleDOI
ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars
Ali Shafiee,Anirban Nag,Naveen Muralimanohar,Rajeev Balasubramonian,John Paul Strachan,Miao Hu,R. Stanley Williams,Vivek Srikumar +7 more
TL;DR: This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner.
Journal ArticleDOI
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories
TL;DR: A tool is designed that carefully models I/O power in the memory system, explores the design space, and gives the user the ability to define new types of memory interconnects/topologies, and a new relay-on-board chip that partitions a DDR channel into multiple cascaded channels is introduced.
Proceedings ArticleDOI
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures
TL;DR: The combination of techniques can address most inefficiencies in SGX memory access and improve overall performance by 3.7×, relative to an SGX baseline, while incurring a memory capacity over-head of only 4.7%.
Proceedings ArticleDOI
MemZip: Exploring unconventional benefits from memory compression
TL;DR: This paper designs a highly simple compressed memory architecture that focuses on complexity, energy, bandwidth, and reliability, and relies on rank subsetting and a careful placement of compressed data and metadata to achieve these benefits.
Proceedings ArticleDOI
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
TL;DR: AFRA as discussed by the authors is a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links, which is designed to be simple, high performance, and robust.