High-efficiency and compact single-phase inverters are desirable in many applications such as solar energy harvesting and electric vehicle chargers. This paper presents a 2-kW, 60-Hz, 450-V $ _{\text{DC}}$ -to-240-V $_{\text{AC}}$ power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge. The inverter features a seven-level flying capacitor multilevel converter, with low-voltage GaN switches operating at 120 kHz. The inverter also includes an active buffer for twice-line-frequency power pulsation decoupling, which reduces the required capacitance by a factor of 8 compared to conventional passive decoupling capacitors, while maintaining an efficiency above 99%. The inverter prototype is a self-contained box that achieves a high power density of 216 W/in $^3$ and a peak overall efficiency of 97.6%, while meeting the constraints including input current ripple, load transient, thermal, and FCC Class B EMC specifications.

A 2-kW Single-Phase Seven-Level Flying Capacitor Multilevel Inverter With an Active Energy Buffer

Capacitive power transfer (CPT) technology is an effective and important alternative to the conventional inductive power transfer (IPT). It utilizes high-frequency electric fields to transfer electric power, which has three distinguishing advantages: negligible eddy-current loss, relatively low cost and weight, and excellent misalignment performance. In recent years, the power level and efficiency of CPT systems has been significantly improved and has reached the power level suitable for electric vehicle charging applications. This paper reviews the latest developments in CPT technology, focusing on two key technologies: the compensation circuit topology and the capacitive coupler structure. The comparison with the IPT system and some critical issues in practical applications are also discussed. Based on these analyses, the future research direction can be developed and the applications of the CPT technology can be promoted.

https://www.mdpi.com/1996-1073/10/11/1752/pdf

A Review on the Recent Development of Capacitive Wireless Power Transfer Technology

This paper proposes a double-sided LC -compensation circuit for a loosely coupled, long-distance capacitive power transfer (CPT) system. A CPT system usually contains two pairs of metal plates as the capacitive coupler. An LC -compensation circuit resonates with the coupler to generate high voltages, and corresponding electric fields, to transfer power. When the compensation circuit is used on both the primary and secondary sides, it results in a double-sided LC -compensated CPT system. The working principle and frequency properties of the CPT system are analyzed. The results show a similarity with the series–series-compensated inductive power transfer system, which has both constant-voltage (CV) and constant-current (CC) working modes. LC -compensation is also compared with LCLC -compensation in terms of power, frequency properties, and output efficiency. A 150-W double-sided LC -compensated CPT prototype is designed and implemented to demonstrate a loosely coupled CPT system with 2.16% coupling coefficient. For both CC and CV working modes, the experimental results achieve dc–dc efficiencies higher than 70% across an air-gap distance of 180 mm with a switching frequency of 1.5 MHz.

A Double-Sided LC-Compensation Circuit for Loosely Coupled Capacitive Power Transfer

We report losses from charging and discharging the parasitic output capacitor, ${\rm C}_{\rm OSS}$ , in Gallium Nitride (GaN) power devices with voltage ratings over 600  ${\rm V}_{\rm DS}$ . These losses are of particular importance in soft-switched circuits used at MHz switching frequencies, where the output capacitance of the device is charged and discharged once per switching cycle during the device's off-time. This process is assumed lossless. We measure ${\rm C}_{\rm OSS}$ losses from 5–35 MHz sine, square, and Class- $\Phi _{2}$ waveshapes in enhancement-mode and cascode devices, and find that losses are present in all tested devices, equal or greater than conduction losses at MHz frequencies, and exponentially increasing with $\mathbf{dV/dt}$ . The cascode device outperforms the e-mode devices under 300 V, but the e-mode devices are preferred above this operating voltage. Furthermore, we show that, within a device family, losses scale linearly with output energy storage. Packaging appears to have only a minor effect on these losses. Finally, we demonstrate 10 MHz, 200 W dc–dc converters with varying device configurations, showing that, even with constant circulating currents, moving to larger devices with lower ${\rm R}_{\rm DS,ON}$ actually degrades efficiency in certain applications due to ${\rm C}_{\rm OSS}$ losses. In the high-voltage, high-frequency range, these reported losses must be optimized simultaneously with conduction losses on a per-application basis.

/pdf/c-oss-losses-in-600-v-gan-power-semiconductors-in-soft-1rstdv35o8.pdf

C OSS Losses in 600 V GaN Power Semiconductors in Soft-Switched, High- and Very-High-Frequency Power Converters

This paper proposes a six-plate capacitive coupler for large air-gap capacitive power transfer to reduce electric field emissions to the surrounding environment. Compared to the conventional four-plate horizontal structure, the six-plate coupler contains two additional plates above and below the inner four-plate coupler to provide a shielding effect. Since there is a capacitive coupling between every two plates, the six-plate coupler results in a circuit model consisting of 15 coupling capacitors. This complex model is first simplified to an equivalent three-port circuit model, and then to a two-port circuit model which is used in circuit analysis and parameter design. This six-plate coupler can eliminate the external parallel capacitor in the previous LCLC topology, which results in the LCL compensation and reduces the system cost. Due to the symmetry of the coupler structure, the voltage between shielding plates is limited, which reduces electric field emissions. Finite element analysis by Maxwell is used to simulate the coupling capacitors and electric field distribution. Compared to the four-plate horizontal and vertical structures, the six-plate coupler can significantly reduce electric field emissions and expand the safety area from 0.9 to 0.1 m away from the coupler in the well-aligned case. A 1.97 kW prototype is implemented to validate the six-plate coupler, which achieves a power density of 1.95 kW/m2 and a dc–dc efficiency of 91.6% at an air-gap of 150 mm. Experiments also show that the output power maintains 65% of the well-aligned value at 300 mm X misalignment, and 49% at 300 mm Y misalignment.

Six-Plate Capacitive Coupler to Reduce Electric Field Emission in Large Air-Gap Capacitive Power Transfer

Multistage matching networks are often utilized to provide voltage or current gains in resonant conversion applications, such as large conversion ratio power converters and wireless power transfer. In the conventional approach, each stage of a multistage matching network is designed to have a purely resistive input impedance and assumed to be loaded by a purely resistive load. This paper introduces an improved design optimization approach for multistage matching networks comprising L-section stages. The proposed design optimization approach explores the possibility of improvement in efficiency of the network by allowing the L-section stages to have complex input and load impedances. A new analytical framework is developed to determine the effective transformation ratio and efficiency of each stage for the case when input and load impedances may be complex. The method of Lagrange multipliers is used to determine the gain and impedance characteristics of each stage in the matching network that maximize overall efficiency. Compared with the conventional design approach for matching networks, the proposed approach achieves higher efficiency, resulting in loss reduction of up to 35% for a three-stage L-section matching network. The theoretical predictions are validated experimentally using a three-stage matching network designed for 1 MHz and 100 W operation.

Improved Design Optimization for High-Efficiency Matching Networks

This paper presents high efficiency de-de converters based on monolithic normally-off GaN half-bridge power stages with integrated gate drivers. A new gate driver circuitry is introduced, which enhances both the power stage efficiency and the converter overall efficiency. While using only n-type transistors in the GaN process, the proposed gate driver maintains low quiescent power consumption by emulating the complementary operation commonly employed in CMOS processes. Level shifting is accomplished using a bootstrap technique, with the bootstrap capacitor and the bootstrap diode integrated on the same chip. A family of monolithic GaN chips has been designed, targeting operation from up to 45 V, delivering up to 16 W of output power, and operating at 20–400 MHz switching frequencies. The GaN chips are verified in synchronous buck converters, demonstrating record peak power stage efficiencies of 95.0% at 20 MHz, 94.2% at 50 MHz, 93.2% at 100 MHz, 86.5% at 200 MHz, and 72.5% at 400 MHz.

High efficiency 20–400 MHz PWM converters using air-core inductors and monolithic power stages in a normally-off GaN process

This paper presents a monolithic multilevel converter realized in a depletion-mode GaN process and intended to operate as a drain supply modulator (DSM) for high efficiency radio-frequency (RF) power amplifiers (PAs). The custom prototype chip includes a four-level power stage with on-chip integrated gate drivers and damping networks designed to mitigate effects of parasitics during output voltage level transitions. An optimization algorithm is described to maximize the drain supply system efficiency using the level voltages and a minimum switching interval as optimization variables. The monolithic multilevel chip is used to construct a four-level converter prototype. Experimental results are presented for tracking 8 MHz sine-wave and 10 MHz LTE envelope signals. The converter output voltage exhibits fast and well damped level-to-level transients. For the 10 MHz LTE envelope signal, the converter achieves greater than 97.3% power stage efficiency at 3.5 W average output power level.

Monolithic multilevel GaN converter for envelope tracking in RF power amplifiers

This paper introduces a very high frequency (VHF) capacitive wireless power transfer architecture capable of achieving very high power transfer densities and high efficiencies. High power density is achieved using an operating frequency of 100 MHz and through appropriate design of matching networks. High efficiency is achieved using a custom designed half-bridge GaN chip with integrated gate drivers. To validate performance of the proposed architecture, a prototype capacitive wireless power transfer system is built and tested. Experimental results demonstrate that the system transfers 2.5 W of power across a 1 pF capacitive interface at a very high power transfer density of 1.1 W/mm2, at close to 90% efficiency.

High power transfer density and high efficiency 100 MHz capacitive wireless power transfer system

This article presents a two-stage automotive LED driver architecture delivering independently regulated output currents to multiple LED strings. The system consists of a multiphase noninverting buck–boost front-end stage, which allows for a wide battery voltage range, followed by high-frequency immittance-network-based LCL-T resonant converters, which operate as current sources over wide output voltage ranges. The two-stage buck–boost + resonant (BB+resonant) architecture takes advantage of the buck and boost capability of both stages, and the flexibility in setting the intermediate bus voltage to minimize losses. Advantages of the BB+resonant architecture include the use of lower voltage rated devices and soft switching in the resonant stage, leading to reduced losses and size. Experimental results are provided for a prototype consisting of a 250-kHz two-phase front-end stage and 2-MHz LCL-T resonant stages delivering independently regulated 1 A currents to four LED strings with $N = 1$ $-$ 18 LEDs. The measured system efficiency is greater than 88% over wide input (8 $-$ 18 V) and output (3–50 V) voltage ranges, with a peak efficiency of 93%.

Alihossein Sepahvand

Papers

Improved Design Optimization for High-Efficiency Matching Networks

High efficiency 20–400 MHz PWM converters using air-core inductors and monolithic power stages in a normally-off GaN process

Monolithic multilevel GaN converter for envelope tracking in RF power amplifiers

High power transfer density and high efficiency 100 MHz capacitive wireless power transfer system

A Two-Stage Automotive LED Driver With Multiple Outputs