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Author

Allan Upham

Other affiliations: GlobalFoundries
Bio: Allan Upham is an academic researcher from IBM. The author has contributed to research in topics: Copper interconnect & Etching (microfabrication). The author has an hindex of 3, co-authored 5 publications receiving 112 citations. Previous affiliations of Allan Upham include GlobalFoundries.

Papers
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Patent
14 Dec 2004
TL;DR: In this paper, a dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material is described.
Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

62 citations

Patent
Allan Upham1
07 Jun 2001
TL;DR: In this article, a method for in-situ cleaning of a throttle valve in a chemical vapor deposition (CVD) system is described. But the present method is restricted to the field of semiconductor device manufacturing.
Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to an apparatus and method for in-situ cleaning of a throttle valve in a chemical vapor deposition (CVD) system. In the exhaust flow control apparatus of the CVD system, which comprises a chamber isolation valve, throttle valve and vacuum pump, means are provided for introducing cleaning gases downstream of the chamber isolation valve and upstream of the throttle valve. Such means may include a cleaning isolation valve connected to a cleaning gas source. Means for generating a reactive plasma of the cleaning gases, just before the throttle valve, may also be provided. During cleaning of the throttle valve, the CVD chamber is isolated, by closing the chamber isolation valve, and cleaning gases are flowed into the throttle valve, by opening the cleaning isolation valve.

43 citations

Patent
16 Jun 2004
TL;DR: In this paper, a method for dual damascene interconnects in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material is described.
Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material (13), then the planarizing material (16) is deposited in the vias and on the dielectric material, and the barrier material (17) is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material (19), etched through the barrier material into the. planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

4 citations

Patent
B. Peethala1, Spyridon Skordas1, Da Song1, Allan Upham1, Kevin R. Winstel1 
10 Jun 2014
TL;DR: In this paper, a method of preparing an etch solution and thinning semiconductor wafers using the solution is proposed, which includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio.
Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×10 19 atoms/cm 3 ; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.

3 citations

Patent
16 Jun 2004
TL;DR: In this article, a method for dual damascene interconnects in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material is described.
Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material (13), then the planarizing material (16) is deposited in the vias and on the dielectric material, and the barrier material (17) is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material (19), etched through the barrier material into the. planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

Cited by
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Patent
Dmitry Lubomirsky1, Qiwei Liang1, Soonam Park1, Kien N. Chuc1, Ellie Yieh1 
30 May 2007
TL;DR: In this article, a system to form a dielectric layer on a substrate from a plasma of reactive reactive precursors is described, which includes a deposition chamber, a substrate stage, and a remote plasma generating system coupled to the deposition chamber.
Abstract: A system to form a dielectric layer on a substrate from a plasma of dielectric precursors is described. The system may include a deposition chamber, a substrate stage in the deposition chamber to hold the substrate, and a remote plasma generating system coupled to the deposition chamber, where the plasma generating system is used to generate a dielectric precursor having one or more reactive radicals. The system may also include a precursor distribution system that includes at least one top inlet and a plurality of side inlets. The top inlet may be positioned above the substrate stage and the side inlets may be radially distributed around the substrate stage. The reactive radical precursor may be supplied to the deposition chamber through the top inlet. An in-situ plasma generating system may also be included to generate the plasma in the deposition chamber from the dielectric precursors supplied to the deposition chamber.

247 citations

Patent
20 Dec 2011
TL;DR: In this paper, a capacitively coupled plasma (CCP) unit is described inside a process chamber, and a pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
Abstract: Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

236 citations

Patent
02 Sep 2004
TL;DR: In this paper, a reaction chamber and a gas distributor are coupled to the inlet to receive a gas flow and a distributor plate including a first surface facing the reaction chamber, a second surface facing a reaction vessel, and a plurality of passageways.
Abstract: Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto microelectronic workpieces. In one embodiment, a reactor for vapor deposition of a material comprises a reaction chamber and a gas distributor. The reaction chamber can include an inlet and an outlet. The gas distributor is positioned in the reaction chamber. The gas distributor has a compartment coupled to the inlet to receive a gas flow and a distributor plate including a first surface facing the compartment, a second surface facing the reaction chamber, and a plurality of passageways. The passageways extend through the distributor plate from the first surface to the second surface. Additionally, at least one of the passageways has at least a partially occluded flow path through the plate. For example, the occluded passageway can be canted at an oblique angle relative to the first surface of the distributor plate so that gas flowing through the canted passageway changes direction as it passes through the distributor plate.

233 citations

Patent
10 Oct 2003
TL;DR: In this paper, the authors describe a plasma unit with a first portion or transmissive portion through which the plasma energy can propagate, a second portion or distributor portion having a plurality of outlets, and a chamber in fluid communication with the plurality of outlet.
Abstract: A reactor comprising an energy source, a plasma unit positioned relative to the energy source, and a processing vessel connected to the plasma unit. The energy source has a generator that produces a plasma energy and a transmitter to transmit the plasma energy. The plasma unit has a first portion or transmissive portion through which the plasma energy can propagate, a second portion or distributor portion having a plurality of outlets, and a chamber in fluid communication with the plurality of outlets. The chamber is generally between or within the first and second portions. The plasma energy can pass through at least the first portion and into the chamber to create a plasma in the chamber. The second portion can also be transmissive or opaque to the plasma energy. The processing vessel includes a workpiece holder across from the outlets of the second portion of the plasma unit.

172 citations

Patent
18 Mar 2004
TL;DR: In this paper, a diffusion barrier on low aspect features of an integrated circuit include at least three operations: the first operation deposits barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit.
Abstract: Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

158 citations