Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >

/pdf/bus-invert-coding-for-low-power-i-o-239mz70mgl.pdf

Bus-invert coding for low-power I/O

This handbook with exercises reveals in formalisms, hitherto mainly used for hardware and software design and verification, unexpected mathematical beauty. The lambda calculus forms a prototype universal programming language, which in its untyped version is related to Lisp, and was treated in the first author's classic The Lambda Calculus (1984). The formalism has since been extended with types and used in functional programming (Haskell, Clean) and proof assistants (Coq, Isabelle, HOL), used in designing and verifying IT products and mathematical proofs. In this book, the authors focus on three classes of typing for lambda terms: simple types, recursive types and intersection types. It is in these three formalisms of terms and types that the unexpected mathematical beauty is revealed. The treatment is authoritative and comprehensive, complemented by an exhaustive bibliography, and numerous exercises are provided to deepen the readers' understanding and increase their confidence using types.

http://types10.mimuw.edu.pl/content/slides/day1/HenkBarendregt.pdf

Lambda Calculus with Types

Bus-invert coding for low-powerI/O

The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology. >

/pdf/an-introduction-to-high-level-synthesis-3rbvfs1uwt.pdf

An Introduction to High-Level Synthesis

This paper surveys the design of embedded computer systems, which use software running on programmable computers to implement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design problem-the design of the hardware and software components influence each other. This paper emphasizes a historical approach to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hardware and software architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design. We also describe design and synthesis techniques for co-design and related problems. >

http://home.engineering.iastate.edu/~zambreno/classes/cpre583/documents/Wol94A.pdf

Hardware-software co-design of embedded systems

High — Level Synthesis

In the previous chapters we have defined synthesis, presented target architectures and design-quality measures, discussed description languages and design representations and presented algorithms for partitioning, scheduling and allocation for synthesis on higher-than-logic abstraction levels. In this chapter we will combine those ideas into a design methodology for synthesis on system and chip levels. System-level synthesis takes a behavioral description of the complete system and generates another behavioral description of the same system in which each custom, semicustom or standard chip is described separately. Chip synthesis converts the behavioral description of each chip into a structural description with register-transfer (RT) components. We will discuss several alternatives for synthesis systems and the technical justification behind approaches taken in those alternatives. The work on design methodology is scarce and no high-level synthesis (HLS) systems are widely used in practice. In this chapter, we mainly discuss requirements for HLS systems and propose possible solutions, sometimes based on our own work but most often based on speculations on the nature of other work in industry and academia.

Design Methodology for High-Level Synthesis

Author(s): Wu, Allen C.H.; Gajski, Daniel | Abstract: SLAM is a structure to layout synthesis system. It incorporates parameterisable bit-sliced and glue-logic generators to produce high density layout. In this paper, we describe a sliced layout architecture and SLAM system. In addition, we present partitioning algorithms for generating the floorplan for such an architecture. The algorithms partition the netlist into component sets best suited for different layout styles such as bit-sliced or strip-oriented logic. Each group is partitioned further into clusters to achieve better area utilization. Several experiments demonstrate that highly dense layouts can be achieved by using these algorithms with the sliced layout architecture.

/pdf/slam-an-automated-structure-to-layout-synthesis-system-125pjo5pdh.pdf

SLAM : an automated structure to layout synthesis system

Author(s): Gajski, Daniel; Lis, Joseph; Zanden, Nels Vander; Wu, Allen | Abstract: This report describes the design process and synthesis tools used in the UC Irvine CADLAB design environment to design a representative benchmark. The steps taken and rationale used in each stage of the design process are discussed. The benchmark is initially described using a VHDL behavioral description; results produced by each intermediate tool are presented, showing the system flow and integration of tools. The final silicon layout is performed in 3 micron CMOS technology.

/pdf/synthesis-from-vhdl-rockwell-counter-case-study-532bgffkbg.pdf

Synthesis from VHDL : Rockwell-counter case study

Author(s): Zanden, Nels Vander; Wu, Allen C.H.; Gajski, Daniel | Abstract: This paper describes a method for incorporating layout parameters to better meet performance contraints. We define an algorithm for synthesis of high-performance designs and present a synthesis tool for use with custom layout generators. Experimental results indicate such an approach produces faster layouts and permits greater area/time tradeoffs than traditional logic synthesis systems.

/pdf/performance-optimization-in-layout-driven-synthesis-3rfav121v2.pdf

Allen C.H. Wu

Papers

High — Level Synthesis

Design Methodology for High-Level Synthesis

SLAM : an automated structure to layout synthesis system

Synthesis from VHDL : Rockwell-counter case study

Performance optimization in layout driven synthesis