A review on monitoring and advanced control strategies for precision irrigation

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

Image Compression aims at minimal the Storage and for the easy transmission Without affecting pictures quality. In this paper HAAR wavelet based Discrete Wavelet Transform (DWT) is done for the effective and efficient image compression..HAAR DWT provides an easy way of compression as the coefficient are either 1 or -1.The wavelet transforms are used for the time and frequency analysis. In this paper higher compression ratio is obtained after three levels of decompositon. The decomposed can be reconstructed without appreciable loss in the original image.

Image compression using HAAR discrete wavelet transform

Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the advanced encryption standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.

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Design and implementation of pipelined and parallel AES encryption systems using FPGA

Now-a-days, multimedia based applications have been developed rapidly. Digital information is easy to process but it allows illegal users to access the data. For protecting the data from this illegal use, Digital Rights Management (DRM) can be used. DRM allows secure exchange of digital data over internet or other electronic media. In this paper, FPGA based implementation of DWT alongwith Advanced Encryption Standard (AES) based watermarking is discussed. With this approach, improved security can be achieved. The complete system is designed using HDL and simulated using Questasim and MATLAB Simulink model. The synthesis result shows that this implementation occupies only 2117 slices and maximum frequency reported for this design is 228.064 MHz.

https://beei.org/index.php/EEI/article/download/651/912

Watermarking and Cryptography Based Image Authentication on Reconfigurable Platform

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

https://ijres.iaescore.com/index.php/IJRES/article/viewFile/17898/pdf

High Speed Area Efficient FPGA Implementation of AES Algorithm

Generally, the data transmitted over any communication channel is affected due to noise. So, for detecting and correcting the errors due to channel noise, encoding and decoding should be performed at the transmitter and receiver end respectively. The Viterbi algorithm is used in many communication channels for decoding convolutional codes. Using VLSI technology, the system requires low power, less area and high speed constraints while designing. Because of different steps for designing Viterbi Decoder speed of designing is limited. In this paper, different kind of implementation of Viterbi decoder along with their performance has been discussed.

Different Approaches For Implementation of Viterbi decoder on reconfigurable platform

Image compression is process of converting an image in such a way that, it should consume less space than original. This is most popular and commercially successful technique in the field of digital image processing. As Discrete Wavelet Transform (DWT) proves most useful technique in image compression and it is also used in a large number of applications for multi-resolution analysis of signals. When we use VLSI technology, we can achieve optimization of area, low power consumption and high speed constraints. In our paper, we have presented efficient way of DWT implementation for image compression which occupies 113 slices at maximum operating frequency of 1102.536 MHz.

An efficient FPGA implementation of discrete wavelet transform for image compression

/pdf/different-approaches-for-implementation-of-viterbi-decoder-445unuvrox.pdf

Altaf O. Mulani

Papers

Watermarking and Cryptography Based Image Authentication on Reconfigurable Platform

High Speed Area Efficient FPGA Implementation of AES Algorithm

Different Approaches For Implementation of Viterbi decoder on reconfigurable platform

An efficient FPGA implementation of discrete wavelet transform for image compression

Different Approaches for Implementation of Viterbi Decoder on Reconfigurable Platform