Ana Isabela Araujo Cunha

Bio: Ana Isabela Araujo Cunha is an academic researcher from Federal University of Bahia. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 9, co-authored 41 publications receiving 499 citations.

An MOS transistor model for analog circuit design

Abstract: This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design

Abstract: Most of the new generation compact models for the MOSFET have many commonalities since they are based on the same main approximations: gradual channel, charge-sheet, and depletion charge linearization. In this study we show that if we include some additional physics-consistent conditions for the MOSFET equations we obtain a very compact model that we call the advanced compact MOSFET (ACM) model. The core ACM model, design-oriented equations, parameter extraction, and a design example are presented.

A current-based model for the MOS transistor

Abstract: This paper presents a physics-based model for the MOS transistor, suitable for circuit design and simulation and valid from weak to strong inversion. Each static or dynamic characteristic is accurately described by a single-piece function of two saturation currents.

An amplifier design methodology derived from a MOSFET current-based model

Abstract: This paper presents a design methodology for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. The design and integration of a common-source amplifier illustrate the appropriateness of the proposed methodology.

Unambiguous Extraction of Threshold Voltage Based on the Transconductance-to-Current Ratio

Abstract: This paper presents a very simple methodology for determining the threshold voltage. The procedure is based on the expressions of the Advanced Compact MOSFET (ACM) model, valid in all regimes of operation, which assures physical meaning, consistency and reliability for the results. The extraction of the threshold voltage is accomplished over a single measured drain current characteristic in the linear region, in order to avoid short channel effects. Experimental results for the extraction of threshold voltages in 0.35 and 0.18µm CMOS tecnhologies are shown.

Design Of Analog Cmos Integrated Circuits

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Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

Abstract: Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Tradeoffs and Optimization in Analog CMOS Design

Abstract: The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.

A 128 $\,\times$ 128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers

Abstract: Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision sensing and processing. They feature unique characteristics such as contrast coding under wide illumination variation, micro-second latency response to fast stimuli, and low output data rates (which greatly improves the efficiency of post-processing stages). They can track extremely fast objects (e.g., time resolution is better than 100 kFrames/s video) without special lighting conditions. Their availability has triggered a new range of vision applications in the fields of surveillance, motion analyses, robotics, and microscopic dynamic observations. One key DVS feature is contrast sensitivity, which has so far been reported to be in the 10-15% range. In this paper, a novel pixel photo sensing and transimpedance pre-amplification stage makes it possible to improve by one order of magnitude contrast sensitivity (down to 1.5%) and power (down to 4 mW), reduce the best reported FPN (Fixed Pattern Noise) by a factor of 2 (down to 0.9%), while maintaining the shortest reported latency (3 μs) and good Dynamic Range (120 dB), and further reducing overall area (down to 30 × 31 μm per pixel). The only penalty is the limitation of intrascene Dynamic Range to 3 decades. A 128 × 128 DVS test prototype has been fabricated in standard 0.35 μm CMOS and extensive experimental characterization results are provided.