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[서평]「Computer Organization and Design, The Hardware/Software Interface」

[발표] 2015개정 실과 교육과정 ‘가정생활’ 영역 개발 방향

http://wpage.unina.it/a.botta/pub/COMNET_WORKLOAD.pdf

A tool for the generation of realistic network workload for emerging networking scenarios

It represents a universally applicable attitude and skill set everyone, not just computer scientists, would be eager to learn and use.

/pdf/computational-thinking-ji-suan-lun-de-si-kao-3qvv34ha3s.pdf

Computational Thinking 計算論的思考

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

http://www.gii.upv.es/web_architecture/download/article-20071126151056-apont.pdf

A user-focused evaluation of web prefetching algorithms

Web prefetching performance metrics: a survey

Web prefetching is a technique that has been researched for years to reduce the latency perceived by users. For this purpose, several web prefetching architectures have been used, but no comparative study has been performed to identify the best architecture dealing with prefetching. This paper analyzes the impact of the web prefetching architecture focusing on the limits of reducing the user?s perceived latency. To this end, the factors that constrain the predictive power of each architecture are analyzed and these theoretical limits are quantified. Experimental results show that the best element of the web architecture to locate a single prediction engine is the proxy, whose implementation could reduce the perceived latency up to 67%. Schemes for collaborative predictors located at diverse elements of the web architecture are also analyzed. These predictors could dramatically reduce the perceived latency, reaching a potential limit of about 97% for a mixed proxy-server collaborative prediction engine.

/pdf/the-impact-of-the-web-prefetching-architecture-on-the-limits-340mglw9le.pdf

The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency

Web prefetching is one of the techniques proposed to reduce user's perceived latencies in the World Wide Web The spatial locality shown by user's accesses makes it possible to predict future accesses based on the previous ones A prefetching engine uses these predictions to prefetch the web objects before the user demands them The existing prediction algorithms achieved an acceptable performance when they were proposed but the high increase in the amount of embedded objects per page has reduced their effectiveness in the current web In this paper we show that most of the predictions made by the existing algorithms are useless to reduce the user's perceived latency because these algorithms do not take into account how current web pages are structured, ie, an HTML object with several embedded objects Thus, they predict the accesses to the embedded objects in an HTML after reading the HTML itself For this reason, the prediction advance is not enough to prefetch the objects and therefore there is no latency reduction As a result of a wide analysis of the behaviour of the most commonly used algorithms, in this paper we present the DDG algorithm that distinguishes between container objects (HTML) and embedded objects to create a new prediction model according to the structure of the current web Results show that, for the same amount of extra requests to the server, DDG always outperforms the existing algorithms by reducing the perceived latency between 15% and 150% more without increasing the computing complexity

/pdf/ddg-an-efficient-prefetching-algorithm-for-current-web-4jz7al6sx2.pdf

Ana Pont

Papers

A user-focused evaluation of web prefetching algorithms

Web prefetching performance metrics: a survey

The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency

DDG: An Efficient Prefetching Algorithm for Current Web Generation

Dweb model: Representing Web 2.0 dynamism