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Anbalagan Karthikeyan

Bio: Anbalagan Karthikeyan is an academic researcher from National Institute of Technology, Karnataka. The author has contributed to research in topics: Harmonic & Symmetrical components. The author has an hindex of 1, co-authored 1 publications receiving 24 citations.

Papers
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Journal ArticleDOI
TL;DR: An enhanced control strategy for DVR using dual role cascaded delay signal cancellation (CDSC)-based dual vector control (DVC) under unbalanced and distorted grid conditions is presented.
Abstract: For the effective operation of a dynamic voltage restorer (DVR), a control strategy plays a significant role. This paper presents an enhanced control strategy for DVR using dual role cascaded delay signal cancellation (CDSC)-based dual vector control (DVC) under unbalanced and distorted grid conditions. Based on the numerical analysis, it is found that the CDSC prefilter is a promising solution when grid voltage is distorted by symmetric, asymmetric harmonics, and unbalanced sag. Mainly, the CDSC prefilter extracts instantaneous symmetrical components of the grid voltage required for voltage sags detection and generation of fundamental component of reference voltage for the DVR. A CDSC-based DVC algorithm with inductor current and capacitor voltage feedback is implemented in a synchronous reference frame, which tracks the fundamental DVR reference voltages. An extractor based on the modified CDSC strategy is designed to extract harmonics from load voltage during distorted grid conditions. These extracted harmonic components (nonfundamental) are added in phase opposition with fundamental component and fed to pulse width modulation block to generate reference voltages. Experimental studies are conducted on scaled down (100 V, 0.5 kVA) laboratory prototype DVR to verify the effectiveness of the proposed control algorithm under unbalanced and distorted grid conditions.

30 citations


Cited by
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Journal ArticleDOI
TL;DR: An efficient strategy to improve the voltage quality of sensitive loads with the optimal utilization of a dynamic voltage restorer (DVR) based on energy-optimized compensation strategies and completes the smooth transition of the transient process during the voltage compensation and recovery stages.
Abstract: This paper introduces an efficient strategy to improve the voltage quality of sensitive loads with the optimal utilization of a dynamic voltage restorer (DVR). Traditional control strategies mainly focus on the voltage compensation stage to reduce the voltage rating of the DVR or minimize the required capacity of the energy storage device. In addition, the phase jump correction in the early stage of the compensation has attracted more attention as well. In reality, phase jump issues may occur in the initial and final stages of compensation, and they must be avoided for most loads, but few works focus on how a DVR can smoothly exit the system after the fault elimination. With the main objective of mitigating the phase jump in the load side voltage while improving the overall sag compensation time, this paper demonstrates that: 1) based on energy-optimized compensation strategies, the proposed approach aims at completing the smooth transition of the transient process during the voltage compensation and recovery stages and ensuring effective linkage from the former to the latter and 2) the mode operation boundaries in the two stages are derived and compared, and the updated procedure of a new injected reference voltage is activated to prevent the system from going outside its operating limits. Furthermore, the operation logic and the overall control scheme are elaborated, which ensure that the proposed approach preserves superior controllability to provide flexible voltage support. Finally, a combination of simulation and experimental results is used to validate the performance of the proposed method.

30 citations

Journal ArticleDOI
TL;DR: Three different heuristic strategies are proposed for reconfiguration problem which can provide Total Harmonic Distortion minimization with the lowest calculation burden and the effective harmonic reduction using the proposed methods is provided with much lower calculation burden comparing to the meta-heuristic solution strategies.

20 citations

Journal ArticleDOI
TL;DR: The recursive-form structures of MDSC operators are analyzed and are found to be simple in implementation when compared to direct-form realizations, which means that these operators can provide more flexibility to configure the delay time and undesired harmonics in comparison with the existing cascaded delayed signal cancellation operators.
Abstract: Phase-locked loops (PLLs) are widely utilized for grid synchronization and control of power electronic converters. More recently, both in-loop-filtered- and prefiltered-based PLLs have become more popular due to their prompt and accurate estimations of grid voltage quantities. In the past, an advanced filter viz., multiple delayed signal cancellation (MDSC) operators, has been successfully investigated in both $\alpha \beta$ -frame and $dq$ -frame for extracting fundamental-frequency positive-sequence grid voltage quantities by using conventional synchronous reference frame PLL. These operators can provide more flexibility to configure the delay time and undesired harmonics in comparison with the existing cascaded delayed signal cancellation operators. In this paper, the recursive-form structures of MDSC operators are analyzed, which are derived from the direct-form MDSC realizations. The recursive-form structures of MDSC operators are simple in implementation when compared to direct-form realizations. With the recursive-form MDSC implementations, both prefiltered MDSC-PLL and in-loop filtered MDSC-PLL will be investigated in detail. The design guidelines of these recursive-form-based MDSC-PLLs are presented. Comparison studies of the proposed PLLs and the validation of their dynamic performances are done by experimental verifications.

18 citations

Journal ArticleDOI
01 Jan 2021
TL;DR: This article addresses the issues in conventional P and PI multiloop controller with and without feedforward path then proposes PDF control strategy for DVR and shows the efficacy and robustness of the proposed controller for D VR under symmetric and asymmetric voltage sags.
Abstract: Grid integration of distributed energy resources has become a technical challenge in the distribution network operation due to the intermittent nature of renewable energy sources and their impact on grid voltage stability. Thus, a dynamic voltage restorer (DVR) is installed in the distribution network system to reduce such grid voltage impact on sensitive loads. In this article, a pseudo-derivative-feedback (PDF)-based voltage controller is implemented for the effective operation of DVR under voltage disturbances. Response of DVR primarily depends upon its controller action. This article addresses the issues in conventional P and PI multiloop controller with and without feedforward path then proposes PDF control strategy for DVR. Using the proposed controller, dynamic performance of DVR is improved. The efficacy of the proposed controller is illustrated by a comparative study with conventional P and PI controller using time response and relative stability analysis. Finally, PSCAD simulation studies for a 10 kV medium voltage DVR and experimental results using a low voltage laboratory prototype DVR are presented to prove the robustness of proposed controller for DVR under symmetric and asymmetric voltage sags.

17 citations

Journal ArticleDOI
TL;DR: The improved FCL-DVR using energy-optimized control strategy can not only perform the dual functions well, but also achieve the capacity optimization of FCL -DVR key components.
Abstract: Fault current-limiting dynamic voltage restorers (FCL-DVRs), also named as dual-functional DVRs, involving both the FCL and the voltage compensation (VC) function, have attracted more attention. However, in case of the FCL-DVR operating in VC mode, either the high capacity of storage system in the dc-link or the oversizing of power converter is needed, and in case of the FCL-DVR operating in FCL mode both the high dc-link voltage and the oversizing of power converter are needed. Thus, in order to overcome these drawbacks, an improved FCL-DVR, which consists of an LC filter coupled with series coupling capacitor (LCC) at the ac side, is proposed in this article. The improved FCL-DVR using energy-optimized control strategy can not only perform the dual functions well, but also achieve the capacity optimization of FCL-DVR key components. The operating principle and performance of the proposed FCL-DVR under FCL and VC mode are elaborated, respectively. The optimal design of LCC and selection of FCL branch are studied in detail to ensure high stability and reliability for the proposed FCL-DVR operating in both modes. The simulation and experimental results clearly validate the effectiveness of the proposed topology and method.

15 citations