Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

The ever-increasing demand for security in portable energy-constrained environments that lack a coherent security architecture has resulted in the need to provide energy-efficient algorithm-agile cryptographic hardware. Domain-specific reconfigurability is utilized to provide the required flexibility, without incurring the high overhead costs associated with generic reprogrammable logic. The resulting implementation is capable of performing an entire suite of cryptographic primitives over the integers modulo N, binary Galois fields and nonsupersingular elliptic curves over GF(2/sup n/), with fully programmable moduli, field polynomials and curve parameters ranging in size from 8 to 1024 bits. The resulting processor consumes a maximum of 75 mW when operating at a clock rate of 50 MHz and a 2-V supply voltage. In ultralow-power mode (3 MHz at 0.7 V) the processor consumes at most 525 /spl mu/W. Measured performance and energy efficiency indicate a comparable level of performance to previously reported dedicated hardware implementations, while providing all of the flexibility of a software-based implementation. In addition, the processor is two to three orders of magnitude more energy efficient than optimized software and reprogrammable logic-based implementations.

/pdf/an-energy-efficient-reconfigurable-public-key-cryptography-2o8ggaivnh.pdf

An energy-efficient reconfigurable public-key cryptography processor

It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operand and modulus. Unlike previous approaches, we systematically implement and compare several variants of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture. The results allow conclusions about the feasibility and time-space trade-offs of our architecture for implementation on Xilinx XC4000 series FPGAs. As a major practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.

Montgomery modular exponentiation on reconfigurable hardware

Memristors are passive electrical components that can act like simple memories. Here, the authors use an array of hafnium oxide memristors to create a type of artificial neural network, known as a Hopfield network, that is capable of retrieving data from partial information

/pdf/associative-memory-realized-by-a-reconfigurable-memristive-25s3lz8d7o.pdf

Associative memory realized by a reconfigurable memristive Hopfield neural network

This paper describes new methods for producing optimal binary signed-digit representations. This can be useful in the fast computation of exponentiations. Contrary to existing algorithms, the digits are scanned from left to right (i.e., from the most significant position to the least significant position). This may lead to better performances in both hardware and software.

Optimal left-to-right binary signed-digit recoding

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

An implementation of a VLSI fully interconnected neural network with only two binary memory points per synapse is described. The small area of single synaptic cells allows implementation of neural networks with hundreds of neurons. Classical learning algorithms like the Hebb's rule show a poor storage capacity, especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection; an algorithm for programming a Hopfield neural network as a high-storage content-addressable memory is proposed. The storage capacity obtained with this algorithm is very promising for pattern-recognition applications. >

/pdf/neural-networks-for-high-storage-content-addressable-memory-3dib5i1hwe.pdf

Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm

J.J. Hopfield's neural networks (1982) show retrieval and speed capabilities that make them good candidates for content-addressable memories (CAMs) in problems such as pattern recognition and optimization. A novel implementation is presented of a VLSI fully interconnected neural network with only two binary memory points per synapse (the connection weights are restricted to three different values: +1, 0 and -1). The small area of single synaptic cells (about 10/sup 4/ mu m/sup 2/) allows the implementation of neural networks with more than 500 neurons. Because of the poor storage capability of D. Hebb's learning rule (1949), especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection, a novel algorithm is proposed for programming a Hopfield neural network as a high-storage-capacity CAM. The results of the VLSI circuit programmed with this algorithm are very promising for pattern-recognition applications. >

/pdf/a-high-storage-capacity-content-addressable-memory-and-its-2njo2ak2i1.pdf

A high-storage capacity content-addressable memory and its learning algorithm

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 μm CMOS process and 500 mW at 25 MHz).

/pdf/a-single-chip-1024-bits-rsa-processor-2qi66bk1yd.pdf

Andre Vandemeulebroecke

Papers

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm

A high-storage capacity content-addressable memory and its learning algorithm

A single chip 1024 bits RSA processor

An algorithm for pattern recognition with VLSI neural networks