Andrea Baschirotto

Bio: Andrea Baschirotto is an academic researcher from University of Milano-Bicocca. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 41, co-authored 611 publications receiving 8233 citations. Previous affiliations of Andrea Baschirotto include Ericsson & Istituto Nazionale di Fisica Nucleare.

Behavioral modeling of switched-capacitor sigma-delta modulators

Abstract: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Abstract: Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.

The L3 silicon microvertex detector

Abstract: The design and construction of the silicon strip microvertex detector (SMD) of the L3 experiment at LEP are described. We present the sensors, readout electronics, data acquisition system, mechanical assembly and support, displacement monitoring systems and radiation monitoring system of the recently installed double-sided, double-layered SMD. This detector utilizes novel and sophisticated techniques for its readout.

A 1 V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing

Abstract: The switched-capacitor technique which implements analog functions in CMOS technology requires capacitors, switches, and opamps. Supply voltage reduction does not affect capacitors. On the other hand, turning MOS switches on and off and maintaining proper opamp operation are difficult with reduced supply voltage. Reducing the supply voltage reduces MOS switch overdrive so complementary switches are not effective. Three solutions have been proposed: low-threshold devices, on-chip voltage multipliers, and switched-opamps. Technologies with low-threshold devices are costly. On-chip voltage multiplication is not possible in scaled-down technologies where devices cannot sustain the multiplied voltage. Switched opamps have the potential to solve the problem by eliminating critical switches in series with opamp output nodes and realizing their function by turning the opamp on and off. The authors present the structure of a prototype biquad band-pass filter (with fo/fs=0.25 and Q=7) implemented in 0.5 /spl mu/m CMOS technology. The area is about 0.15 mm/sup 2/ and the unit capacitance is 0.25 pF. The filter consumes about 160 /spl mu/W.

Modeling sigma-delta modulator non-idealities in SIMULINK(R)

Abstract: This paper presents a complete set of SIMULINK(R) models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed. The proposed set of models takes into account most of the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier parameters (noise, finite gain, finite bandwidth, slew-rate and saturation voltages). For each model we present a description of the considered effect as well as all of the implementative details. Simulation results on a second-order switched-capacitor sigma-delta modulator demonstrate the validity of the models proposed.

The ATLAS Experiment at the CERN Large Hadron Collider

Abstract: This paper describes the ATLAS experiment as installed in i ts experimental cavern at point 1 at CERN. It also presents a brief overview of the expec ted performance of the detector.

Averages of b-hadron, c-hadron, and tau-lepton properties as of early 2012

Abstract: This article reports world averages of measurements of b-hadron, c-hadron, and tau-lepton properties obtained by the Heavy Flavor Averaging Group (HFAG) using results available through the end of 2011. In some cases results available in the early part of 2012 are included. For the averaging, common input parameters used in the various analyses are adjusted (rescaled) to common values, and known correlations are taken into account. The averages include branching fractions, lifetimes, neutral meson mixing parameters, CP violation parameters, parameters of semileptonic decays and CKM matrix elements.