Andrea Calimera

Bio: Andrea Calimera is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 18, co-authored 135 publications receiving 1127 citations. Previous affiliations of Andrea Calimera include University of Bologna & Instituto Politécnico Nacional.

NBTI-aware power gating for concurrent leakage and aging optimization

Abstract: Power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on small devices and scaled supply voltages. The emergence of Negative Bias Temperature Instability (NBTI) as the most relevant source of unreliability in sub-90nm technologies has even exacerbated this incompatibility of the two metrics: NBTI manifests itself as an increase of the propagation delay over time, which adds up to the delay penalty introduced by most low-power design solutions. In this work, we show how the most widely adopted leakage reduction solution, that is, power-gating, can overcome this conflict, and how it can be used to naturally reduce the effects of NBTI on delay. Based on this important property, we present a methodology for NBTI-aware power gating that allows synthesizing low-leakage circuits with maximum lifetime.

The Human Brain Project and neuromorphic computing.

Abstract: Understanding how the brain manages billions of processing units connected via kilometers of fibers and trillions of synapses, while consuming a few tens of Watts could provide the key to a completely new category of hardware (neuromorphic computing systems). In order to achieve this, a paradigm shift for computing as a whole is needed, which will see it moving away from current “bit precise” computing models and towards new techniques that exploit the stochastic behavior of simple, reliable, very fast, low-power computing devices embedded in intensely recursive architectures. In this paper we summarize how these objectives will be pursued in the Human Brain Project.

Design Techniques and Architectures for Low-Leakage SRAMs

Abstract: In high performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for memory devices, for two main reasons. First, memories have historically been designed with performance as the primary figure of merit; therefore, they are intrinsically non power-efficient structures. Second, memories are accessed in small chunks, thus leaving the vast majority of the memory cells unaccessed for a large fraction of the time. In this paper, we present an overview of the techniques proposed both in the academic and in the industrial domain for minimizing leakage power, and in particular, the subthreshold component, in SRAMs. The surveyed solutions range from cell-level techniques to architectural solutions suitable to system-level design.

Design Techniques for NBTI-Tolerant Power-Gating Architectures

Abstract: While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger -drop effect on the virtual- rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efficient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach.

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

Abstract: Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We propose a new reactivation solution that helps in controlling power supply fluctuations and achieving minimum reactivation times. Our structure limits the turn-on current below a given threshold through a sequential activation of the sleep transistors (STs), which are connected in parallel and sized using a novel optimal sizing algorithm. We also introduce a distributed physical implementation, which allows minimum layout disruption after ST insertion and minimizes routing congestion.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Abstract: High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Ultrathin epitaxial graphite: 2D electron gas properties and a route toward graphene-based nanoelectronics

Abstract: We have produced ultrathin epitaxial graphite films which show remarkable 2D electron gas (2DEG) behavior. The films, composed of typically 3 graphene sheets, were grown by thermal decomposition on the (0001) surface of 6H-SiC, and characterized by surface-science techniques. The low-temperature conductance spans a range of localization regimes according to the structural state (square resistance 1.5 kOhm to 225 kOhm at 4 K, with positive magnetoconductance). Low resistance samples show characteristics of weak-localization in two dimensions, from which we estimate elastic and inelastic mean free paths. At low field, the Hall resistance is linear up to 4.5 T, which is well-explained by n-type carriers of density 10^{12} cm^{-2} per graphene sheet. The most highly-ordered sample exhibits Shubnikov - de Haas oscillations which correspond to nonlinearities observed in the Hall resistance, indicating a potential new quantum Hall system. We show that the high-mobility films can be patterned via conventional lithographic techniques, and we demonstrate modulation of the film conductance using a top-gate electrode. These key elements suggest electronic device applications based on nano-patterned epitaxial graphene (NPEG), with the potential for large-scale integration.