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Author

Andreas Kerber

Other affiliations: Advanced Micro Devices
Bio: Andreas Kerber is an academic researcher from GlobalFoundries. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 19, co-authored 77 publications receiving 1502 citations. Previous affiliations of Andreas Kerber include Advanced Micro Devices.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors summarized recent advances in the understanding of charge trapping and defect generation in HfO2/TiN gate stacks and discussed test procedures specifically tailored to quantify gate stack reliability.
Abstract: It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.

166 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

107 citations

Proceedings ArticleDOI
26 Apr 2009
TL;DR: In this article, a percolation model with different defect generation rates in the HK layer and interfacial SiO x layer that form the stack is explained by a defect distribution model, which impacts the statistics of breakdown of the stack and bimodal distributions are obtained with a transition from a shallow to steep Weibull slope for large areas.
Abstract: Time-dependent dielectric breakdown (TDDB) in high-k (HK) dielectric stacks is characterized by short breakdown times and shallow Weibull slopes. In this work, these observations are explained by a percolation model with different defect generation rates in the HK layer and interfacial SiO x layer that form the stack. The difference in defect generation rate impacts the statistics of breakdown of the stack and bimodal distributions are obtained with a transition from a shallow to steep Weibull slope for large areas. It is shown that for a HK layer with a low initial defect density, long breakdown times and steep Weibull slopes are obtained for typical product areas, mitigating TDDB as a reliability show-stopper for HK dielectrics.

106 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this paper, a case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric.
Abstract: Experimental reliability trends indicate that t inv -scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing t inv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.

97 citations

Proceedings ArticleDOI
26 Apr 2009
TL;DR: In this article, the stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2/TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage.
Abstract: The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ∼ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ∼ dV t 3. Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects –such as oxygen vacancy – and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

93 citations


Cited by
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Journal ArticleDOI
K. Kuhn1
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

558 citations

Journal ArticleDOI
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

512 citations

Journal ArticleDOI
TL;DR: The present review summarizes the basic principles of how to model stochastic defect transitions with a particular focus on multi-state defects and introduces the relatively simple semiclassical approximation of multiphonon theory, which already provides a much better description.

433 citations

Journal ArticleDOI
TL;DR: In this article, different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data.
Abstract: Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

266 citations

Journal ArticleDOI
TL;DR: In this article, the kinetics of charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse $I$ − $V_{G}$ technique.
Abstract: Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse $I_{D}$ – $V_{G}$ technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated.

220 citations