Showing papers by "Andrei Z. Broder published in 1987"

On the second eigenvalue of random regular graphs

Abstract: Expanders have many applications in Computer Science. It is known that random d-regular graphs are very efficient expanders, almost surely. However, checking whether a particular graph is a good expander is co-NP-complete. We show that the second eigenvalue of d-regular graphs, λ2, is concentrated in an interval of width O(√d) around its mean, and that its mean is O(d3/4). The result holds under various models for random d-regular graphs. As a consequence a random d-regular graph on n vertices, is, with high probability a certifiable efficient expander for n sufficiently large. The bound on the width of the interval is derived from martingale theory and the bound on E(λ2) is obtained by exploring the properties of random walks in random graphs.

Efficient fault—tolerant routings in networks

Abstract: We analyze the problem of constructing a network with a given number of nodes which has a fixed routing and which is highly fault tolerant. A construction is presented which forms a “product route graph” from two or more constituent “route graphs.” The analysis involves the surviving route graph , which consists of all nonfaulty nodes in the network with two nodes being connected by a directed edge iff the route from the first to the second is still intact after a set of component failures. The diameter of the surviving route graph is a measure of the worst-case performance degradation caused by the faults. The number of faults tolerated, the diameter, and the degree of the product graph are related in a simple way to the corresponding parameters of the constituent graphs. In addition, there is a “padding theorem” which allows one to add nodes to a graph and to extend a previous routing.

Placing Tiles in the Plane

Abstract: The VLSI placement problem consists of finding an optimum placement of the VLSI components in the plane of the chip A standard optimization goal is to minimize the total amount of space occupied by the wires on the chip We model the VLSI placement problem by considering the problem of placing tiles on the plane when each tile has a preassigned area into which it must be placed We show that for most cases this problem appears computationally infeasible, and we present some fast algorithms for some special cases