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Anees Ullah

Bio: Anees Ullah is an academic researcher from University of Engineering and Technology, Peshawar. The author has contributed to research in topics: Field-programmable gate array & Control reconfiguration. The author has an hindex of 8, co-authored 31 publications receiving 213 citations. Previous affiliations of Anees Ullah include City University of Science and Information Technology & Case Western Reserve University.

Papers
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Journal ArticleDOI
TL;DR: An efficient protection technique is proposed and evaluated showing that it can provide an efficient protection with a lower resource usage than the traditional triple modular redundancy approach.
Abstract: A Viterbi decoder is used in many communication receivers to efficiently decode the received signal that has been convolutional encoded in the transmitter This decoding corrects errors that occur due to noise and other imperfections in the channel and is key to achieve a low bit error rate If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced soft errors can affect the operation of the Viterbi decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured This makes the protection of Viterbi decoders implemented on SRAM-based FPGAs an important issue In this paper, first, fault injection experiments are conducted to study the effects of soft errors on the configuration memory of an SRAM-FPGA implemented Viterbi decoder Then, an efficient protection technique is proposed and evaluated showing that it can provide an efficient protection with a lower resource usage than the traditional triple modular redundancy approach

8 citations

Journal ArticleDOI
TL;DR: This paper presents an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes and exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGAs slice.
Abstract: Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.

8 citations

Journal ArticleDOI
TL;DR: The results demonstrate an evident reduction of the recovery time due to fast error detection time and selective partial reconfiguration of faulty domains, and the methodology drastically reduces Cross-Domain Errors in Look-Up Tables and routing resources.
Abstract: The rapid adoption of FPGA-based systems in space and avionics demands dependability rules from the design to the layout phases to protect against radiation effects. Triple Modular Redundancy is a widely used fault tolerance methodology to protect circuits against radiation-induced Single Event Upsets implemented on SRAM-based FPGAs. The accumulation of SEUs in the configuration memory can cause the TMR replicas to fail, requiring a periodic write-back of the configuration bit-stream. The associated system downtime due to scrubbing and the probability of simultaneous failures of two TMR domains are increasing with growing device densities. We propose a methodology to reduce the recovery time of TMR circuits with increased resilience to Cross-Domain Errors. Our methodology consists of an automated tool-flow for fine-grain error detection, error flags convergence and non-overlapping domain placement. The fine-grain error detection logic identifies the faulty domain using gate-level functions while the error flag convergence logic reduces the overwhelming number of flag signals. The non-overlapping placement enables selective domain reconfiguration and greatly reduces the number of Cross-Domain Errors. Our results demonstrate an evident reduction of the recovery time due to fast error detection time and selective partial reconfiguration of faulty domains. Moreover, the methodology drastically reduces Cross-Domain Errors in Look-Up Tables and routing resources. The improvements in recovery time and fault tolerance are achieved at an area overhead of a single LUT per majority voter in TMR circuits.

7 citations

Proceedings ArticleDOI
20 Oct 2014
TL;DR: The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations and the method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing.
Abstract: Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.

7 citations

Journal ArticleDOI
TL;DR: The presented methodology ensures safe fault injection in BRAM contents while preserving the state of other memory elements of the design by using a one-time generated partial bitstream.
Abstract: On-chip block memories (BRAMs) in SRAM-based FPGAs store critical state information as well as user data which need to be protected against radiation-induced upsets. Therefore, reliability evaluation techniques and upset injection in system components are vital. Previous approaches to fault injection in BRAMs are limited in their abilities to create multiple cell upsets (MCUs) (and, in particular, a kind of MCU called multiple bit upsets) and are vulnerable to unintended state corruption in other memory elements when on-chip injectors are used. This letter proposes an efficient approach for multiple upsets emulation in BRAM contents exploiting the configuration memory cells responsible for initialization. The presented methodology ensures safe fault injection in BRAM contents while preserving the state of other memory elements of the design by using a one-time generated partial bitstream. The approach does not require the time-consuming bitstream generation process for every fault but rather uses run-time single-frame modifications for injection purposes.

7 citations


Cited by
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Journal ArticleDOI
01 Sep 1986
TL;DR: This chapter discusses algorithmics and modular computations, Theory of Codes and Cryptography (3), and the theory and practice of error control codes (3).
Abstract: algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

597 citations

01 Jul 1987

277 citations

Journal ArticleDOI
TL;DR: New ternary circuits aiming to lower the power delay product (PDP) to save battery consumption and the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages are proposed.
Abstract: Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary NAND (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (V dd and V dd /2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively.

74 citations

Journal ArticleDOI
TL;DR: The structure regulator for the perturbations attenuation which is based on the infinite structure regulator is studied and it is applied to a quadrotor which maintains the horizontal position with respect to the earth for the step and sine perturbation.
Abstract: In this work, we study the structure regulator for the perturbations attenuation which is based on the infinite structure regulator. The structure regulator is able to attenuate the perturbations if the transfer function of the departures and perturbations has a numerical value almost equal to zero, and it does not require the perturbations to attenuate them. We apply the structure regulator and the infinite structure regulator to a quadrotor which maintains the horizontal position with respect to the earth for the step and sine perturbations.

72 citations

Journal ArticleDOI
TL;DR: The simulation and experimental results show the superiorities of the proposed method in terms of faster convergence, better tracking precision and better anti-disturbance rejection properties of this enhanced SMC.
Abstract: This paper investigates speed regulation of permanent magnet synchronous motor (PMSM) system based on sliding mode control (SMC). Sliding mode control has been vastly applied for speed control of PMSM. However, continuous SMC enhancement studies are executed to improve the performance of conventional SMC in terms of tracking and disturbance rejection properties as well as to reduce chattering effects. By introducing fractional calculus in the sliding mode manifold, a novel fractional order sliding mode controller is proposed for the speed loop. The proposed fractional order sliding mode speed controller is designed with a sliding surface that consists of both fractional differentiation and integration. Stability of the proposed controller is proved using Lyapunov stability theorem. The simulation and experimental results show the superiorities of the proposed method in terms of faster convergence, better tracking precision and better anti-disturbance rejection properties. In addition, chattering effect of this enhanced SMC is smaller compared to those of conventional SMC. Last but not least, a comprehensive comparison table summarizes key performance indexes of the proposed controller with respect to conventional integer order controller.

70 citations