Ángel Rodríguez-Vázquez

Bio: Ángel Rodríguez-Vázquez is an academic researcher from Spanish National Research Council. The author has contributed to research in topics: CMOS & Chip. The author has an hindex of 44, co-authored 558 publications receiving 7855 citations. Previous affiliations of Ángel Rodríguez-Vázquez include Hungarian Academy of Sciences & University of Tehran.

Nonlinear switched capacitor 'neural' networks for optimization problems

Abstract: A systematic approach is presented for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques. The method is based on formulating a dynamic gradient system whose state evolves in time toward the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed techniques. >

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs

Abstract: Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-/spl mu/m standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3/spl times/3 neighborhoods in less than 1.5 /spl mu/s, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 /spl mu/s, and CNN-like temporal evolutions with a time constant of about 0.5 /spl mu/s. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

Top-Down Design of High-Performance Sigma-Delta Modulators

Abstract: 1. Introduction. 2. Oversampling Sigma-Delta A/D Converters: Basic Concepts and State of the Art. 3. Modeling of Error Mechanisms in Sigma-Delta Modulators. 4. Behavioral Simulation of Sigma-Delta Modulators. 5. SDOPT+FRIDGE: Tools for the Automatic Design of Sigma-Delta Modulators. 6. Integrated Circuit Design (I): A 17-bit 40k Sample/s Fourth-Order Cascade Sigma-Delta Modulator. 7. Integrated Circuit Design (II): A 13-bit 2.2MSample/s Fourth-Order Cascade Multi-Bit Sigma-Delta Modulator. References. Appendix. Index.

Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

Abstract: A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

Operational transconductance amplifier-based nonlinear function syntheses

Abstract: It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirmed. >

Neuromorphic Silicon Neuron Circuits

Abstract: Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

The double scroll family

Abstract: This paper provides a rigorous mathematical proof that the double scroll is indeed chaotic. Our approach is to derive a linearly equivalent class of piecewise-linear differential equations which includes the double scroll as a special case. A necessary and sufficient condition for two such piecewise-linear vector fields to be linearly equivalent is that their respective eigenvalues be a scaled version of each other. In the special case where they are identical, we have exact equivalence in the sense of linear conjugacy. An explicit normalform equation in the context of global bifurcation is derived and parametrized by their eigenvalues. Analytical expressions for various Poincare maps are then derived and used to characterize the birth and the death of the double scroll, as well as to derive an approximate one-dimensional map in analytic form which is useful for further bifurcation analysis. In particular, the analytical expressions characterizing various half-return maps associated with the Poincare map are used in a crucial way to prove the existence of a Shilnikov-type homoclinic orbit, thereby establishing rigorously the chaotic nature of the double scroll. These analytical expressions are also fundamental in our in-depth analysis of the birth (onset of the double scroll) and death (extinction of chaos) of the double scroll. The unifying theme throughout this paper is to analyze the double scroll system as an unfolding of a large family of piecewise-linear vector fields in R^3 . Using this approach, we were able to prove that the chaotic dynamics of the double scroll is quite common, and is robust because the associated horseshoes predicted from Shilnikov's theorem are structurally stable. In fact, it is exhibited by a large family (in fact, infinitely many linearlyequivalent circuits) of vector fields whose associated piecewise-linear differential equations bear no resemblance to each other. It is therefore remarkable that the normalized eigenvalues, which is a local concept, completely determine the system's global qualitative behavior.

Neural networks for nonlinear programming

Abstract: The dynamics of the modified canonical nonlinear programming circuit are studied and how to guarantee the stability of the network's solution. By considering the total cocontent function, the solution of the canonical nonlinear programming circuit is reconciled with the problem being modeled. In addition, it is shown how the circuit can be realized using a neural network, thereby extending the results of D.W. Tank and J.J. Hopefield (ibid., vol.CAS-33, p.533-41, May 1986) to the general nonlinear programming problem. >

The CNN universal machine: an analogic array computer

Abstract: A new invention, the cellular neural network (CNN) universal machine and supercomputer, is presented. This is the first algorithmically programmable analog array computer having real-time and supercomputer power on a single chip. The CNN universal machine is described, emphasizing its programmability as well as global and distributed analog memory and logic, high throughput via electromagnetic waves, and complex cells that may be used also for simulating a broad class of PDEs. Its implementation, the CNN universal chip, is also described, along with its use of a multichip supercomputer. Other types of hardware implementations are also briefly discussed. Details of the algorithmic aspects of the new type of analogic (analog logic) algorithms, as well as the analogic software (language, compiler, machine code, etc.) are explained, along with a brief description of the available CNN workstation for implementing and simulating these new concepts. A broad range of applications is reviewed, including neuromorphic computing, programmable physics, programmable chemistry, and programmable bionics. >