Angelo De Carmine

Bio: Angelo De Carmine is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Low-dropout regulator & Settling time. The author has an hindex of 1, co-authored 2 publications receiving 2 citations.

A Highly Scalable, Time-Based Capless Low-Dropout Regulator using Master-Slave Domino Control

Abstract: An ultra-low quiescent current capacitor-less low-drop out (LDO) regulator is proposed in this paper. The LDO is designed using domino control which automatically increases or decrease the drive strength based on load current. Quiescent current of the proposed LDO also varies with load current hence current consumption is minimized under light load condition. The proposed LDO architecture is fully scalable and can be easily scaled up for higher load currents with almost no design efforts. Implemented in TSMC-65nm, it uses only 1pF of on-chip compensation capacitor and consumes a quiescent current of 11.5µA For an input of 1.2 V and output of 0.9V to 1.1V, settling time of <200ns with undershoot/overshoot of 62mV/40mV for 0–5mA in 100ns load step is achieved 1pF output capacitor.

A Current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS

Abstract: This paper proposes an analog-assisted digital output capacitor-less low-drop out (LDO) regulator. At full load, the digital loop supplies greater than 90% of the load whereas the rest is supplied by the analog loop. The analog loop regulates the output accurately eliminating the limit cycle oscillations and quantization error due to a standalone digital LDO. The analog loop is implemented with a flipped source follower architecture to achieve lower output impedance and higher bandwidth. The digital loop employs 32-bit shift register to control the discrete set of power-FETs. A fast clock (250 MHz) is used to speed up the digital loop during load transients and a slower clock (10 MHz) is used in steady state for power saving. The LDO uses only 1pF as output capacitor and consumes a quiescent current of 17.3μA. The proposed LDO was implemented in TSMC-65nm for an input of 1.2V, output of 1V and achieves settling time less than 110ns with undershoot/overshoot of 24mV/72mV for 0.1–10mA/100ns load step.

A Current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS

Abstract: This paper proposes an analog-assisted digital output capacitor-less low-drop out (LDO) regulator. At full load, the digital loop supplies greater than 90% of the load whereas the rest is supplied by the analog loop. The analog loop regulates the output accurately eliminating the limit cycle oscillations and quantization error due to a standalone digital LDO. The analog loop is implemented with a flipped source follower architecture to achieve lower output impedance and higher bandwidth. The digital loop employs 32-bit shift register to control the discrete set of power-FETs. A fast clock (250 MHz) is used to speed up the digital loop during load transients and a slower clock (10 MHz) is used in steady state for power saving. The LDO uses only 1pF as output capacitor and consumes a quiescent current of 17.3μA. The proposed LDO was implemented in TSMC-65nm for an input of 1.2V, output of 1V and achieves settling time less than 110ns with undershoot/overshoot of 24mV/72mV for 0.1–10mA/100ns load step.

A capless NMOS low-dropout regulator with 15 ns transient response time

Abstract: In this paper, a fast-transient capless NMOS low-dropout regulator (LDO) with low power consumption is proposed. The capacitor multiplier and Super Class-AB operational transconductance amplifier (OTA) with local common mode feedback structure (LCMFB) is employed in the proposed LDO, which not only consumes a small quiescent current but also greatly improves the transient response by increasing the loop bandwidth and charging/discharging current at the gate of the power transistor. Meanwhile, excellent line/load regulation is also achieved by the proposed LDO. The proposed capless LDO was implemented in 0.18 μm CMOS process and the post-layout simulation results show that the transient response of recovery time is only 15 ns, low quiescent current is 11 μA, and line regulation and load regulation are 0.61 mV/V and 7.58 μV/mA respectively.

A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm

Abstract: This brief presents an output-capacitor-free Digital LDO (DLDO) with a novel synthesizable PID controller architecture. The architecture employs multiple asynchronous wave pipelines and a novel differential control loop in parallel with a synchronous fine control. The DLDO is fabricated in a 65nm process and occupies an area of 0.0925mm 2. The DLDO has an output current range of 5mA - 80mA at 50mV dropout and achieves a 93.3ps response time with 99.75% current efficiency resulting in a FOM of 233fs.

Sub-1 V Output-Capacitor-Less Low-Dropout Regulator with Two Compensation Amplifiers for Enhanced Power Supply Rejection

Abstract: In this paper we propose two methods to boost the power supply rejection (PSR) of an output-capacitor-less low-dropout regulator (LDO). Our LDO is targeted for low-power system-on-chip applications, such as medical electronics, RFIDs, and IoT devices, where applied energy harvesting techniques induce large voltage ripple to supply line, thus requiring high PSR out of the LDO. The regulator utilizes a feed-forward path through the amplifier power supply rail to pass-transistor gate. Furthermore it includes a feed-forward amplifier to improve the frequency response and a feedback amplifier to stabilize the LDO, eliminating the need for an area consuming compensation capacitor. The proposed LDO is implemented in 28-nm CMOS technology. It supplies 700-mV output level with a current range of 0–5 mA and a 100-mV dropout voltage. The three amplifiers within our LDO consume only a total of 13 μA, thus regardless of increased complexity, high current efficiency of 99.74% is maintained. At the nominal load of 1 mA, low-frequency PSR reaches a value of −97 dB and at the high-frequency range of 1– 20 MHz PSR is boosted to remain below −20 dB and the region of 3–10 MHz below −30 dB.

A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm

Abstract: This brief presents an output-capacitor-free Digital LDO (DLDO) with a novel synthesizable PID controller architecture. The architecture employs multiple asynchronous wave pipelines and a novel differential control loop in parallel with a synchronous fine control. The DLDO is fabricated in a 65nm process and occupies an area of 0.0925mm 2. The DLDO has an output current range of 5mA - 80mA at 50mV dropout and achieves a 93.3ps response time with 99.75% current efficiency resulting in a FOM of 233fs.