Other affiliations: University of Petroleum and Energy Studies, Ryerson University, Jadavpur University ...read more
Bio: Anirban Sengupta is an academic researcher from Indian Institute of Technology Indore. The author has contributed to research in topics: Design space exploration & High-level synthesis. The author has an hindex of 22, co-authored 233 publications receiving 1930 citations. Previous affiliations of Anirban Sengupta include University of Petroleum and Energy Studies & Ryerson University.
Papers published on a yearly basis
01 Dec 2014
TL;DR: In this paper, a load balancer is deployed in the source node's egress datapath to determine whether the data message is addressed to one of the DCN groups for which the loadbalancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group.
Abstract: Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN.
TL;DR: An overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools is presented to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.
Abstract: Hardware security and trust have become a pressing issue during the last two decades due to the globalization of the semiconductor supply chain and ubiquitous network connection of computing devices. Computing hardware is now an attractive attack surface for launching powerful cross-layer security attacks, allowing attackers to infer secret information, hijack control flow, compromise system root-of-trust, steal intellectual property (IP), and fool machine learners. On the other hand, security practitioners have been making tremendous efforts in developing protection techniques and design tools to detect hardware vulnerabilities and fortify hardware design against various known hardware attacks. This article presents an overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools. By introducing the most recent advances in hardware security research and developments, we aim to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.
TL;DR: A novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs) and experimental results over the standard benchmark indicate an average reduction in final cost of ~12% compared to recent approach.
Abstract: Security against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and incurs extra delay and hardware. This paper proposes a novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs). Proposed approach simultaneously explores an optimal schedule and optimal loop unrolling factor (U) combination for a low cost Trojan security aware DMR schedule. As a specific example, proposed low cost Trojan secured HLS approach relies on particle swarm optimization algorithm to explore optimized Trojan secured schedule with optimal unrolling that provides security against specific Trojan (causing change in computational output) within user provided area and delay constraints. The novel contributions of this paper are, first an exploration of a low cost Trojan security aware HLS solution for loop-based CDFGs; second, proposed encoding scheme for representing design solution comprising candidate schedule resources, candidate loop unrolling factor and candidate vendor allocation information; third, a process for exploring the a low cost vendor assignment that provides Trojan security; finally, experimental results over the standard benchmark that indicates an average reduction in final cost of ~12% compared to recent approach.
•09 May 2013
TL;DR: In this paper, the authors describe a system which provides service switching in a datacenter environment, which can include a service switching gateway which can identify a service tag associated with a received packet.
Abstract: The disclosure herein describes a system, which provides service switching in a datacenter environment. The system can include a service switching gateway, which can identify a service tag associated with a received packet. During operation, the service switching gateway determines a source client, a requested service, or both for the packet based on the service tag, identifies a corresponding service portal based on the service tag, and forwards the packet toward the service portal. The service switching gateway can optionally maintain a mapping between the service tag and one or more of: a source client, a required service, the service portal, and a tunnel encapsulation. The service switching gateway can encapsulate the packet based on an encapsulation mechanism supported by the service portal and forward the packet based on the mapping.
12 Dec 2014
TL;DR: In this paper, the authors provide an elastic architecture for providing a service in a computing system, where the PSN also performs a load balancing operation that assesses the load on each service node, and based on this assessment, has the data messages distributed to the service node(s) in its SN group.
Abstract: Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs.
01 Jan 1972
TL;DR: IoT’s novel factors affecting traditional computer forensics are explored, including its strengths and weaknesses, and several indispensable open research challenges are identified as future research directions.
Abstract: The explosive growth of smart objects and their dependency on wireless technologies for communication increases the vulnerability of Internet of Things (IoT) to cyberattacks. Cyberattacks faced by IoT present daunting challenges to digital forensic experts. Researchers adopt various forensic techniques to investigate such attacks. These techniques aim to track internal and external attacks by emphasizing on communication mechanisms and IoT’s architectural vulnerabilities. In this study, we explore IoT’s novel factors affecting traditional computer forensics. We investigate recent studies on IoT forensics by analyzing their strengths and weaknesses. We categorize and classify the literature by devising a taxonomy based on forensics phases, enablers, networks, sources of evidence, investigation modes, forensics models, forensics layers, forensics tools, and forensics data processing. We also enumerate a few prominent use cases of IoT forensics and present the key requirements for enabling IoT forensics. Finally, we identify and discuss several indispensable open research challenges as future research directions.
01 Jan 2016
TL;DR: This living document is pleased to provide this living document for unlocking the evergrowing vocabulary of abbreviations and acronyms of the telecommunications world.
Abstract: physical design electronics wikipedia in integrated circuit design physical design is a step in the standard design cycle which follows after the circuit design at this step circuit representations of, integrated circuit layout wikipedia integrated circuit layout also known ic layout ic mask layout or mask design is the representation of an integrated circuit in terms of planar geometric shapes, engineering courses concordia university concordia university http www concordia ca content concordia en academics graduate calendar current encs engineering courses html, peer reviewed journal ijera com international journal of engineering research and applications ijera is an open access online peer reviewed international journal that publishes research, telecommunications abbreviations and acronyms consultation erkan is pleased to provide this living document for unlocking the evergrowing vocabulary of abbreviations and acronyms of the telecommunications world, contents international information institute vol 7 no 3 may 2004 mathematical and natural sciences study on bilinear scheme and application to three dimensional convective equation itaru hataue and yosuke
TL;DR: A developed learning model for fast learning network (FLN) based on particle swarm optimization (PSO) has been proposed and named as PSO-FLN, which has outperformed other learning approaches in the testing accuracy of the learning.
Abstract: Supervised intrusion detection system is a system that has the capability of learning from examples about the previous attacks to detect new attacks. Using artificial neural network (ANN)-based intrusion detection is promising for reducing the number of false negative or false positives, because ANN has the capability of learning from actual examples. In this paper, a developed learning model for fast learning network (FLN) based on particle swarm optimization (PSO) has been proposed and named as PSO-FLN. The model has been applied to the problem of intrusion detection and validated based on the famous dataset KDD99. Our developed model has been compared against a wide range of meta-heuristic algorithms for training extreme learning machine and FLN classifier. PSO-FLN has outperformed other learning approaches in the testing accuracy of the learning.
TL;DR: Using an unsupervised clustering analysis, the paper shows that the controllability and observability characteristics of Trojan gates present significant inter-cluster distance from those of genuine gates in a Trojan-inserted circuit, such that Trojan gates are easily distinguishable.
Abstract: This paper presents a novel hardware Trojan detection technique in gate-level netlist based on the controllability and observability analyses. Using an unsupervised clustering analysis, the paper shows that the controllability and observability characteristics of Trojan gates present significant inter-cluster distance from those of genuine gates in a Trojan-inserted circuit, such that Trojan gates are easily distinguishable. The proposed technique does not require any golden model and can be easily integrated into the current integrated circuit design flow. Furthermore, it performs a static analysis and does not require any test pattern application for Trojan activation either partially or fully. In addition, the timing complexity of the proposed technique is an order of the number of signals in a circuit. Moreover, the proposed technique makes it possible to fully restore an inserted Trojan and to isolate its trigger and payload circuits. The technique has been applied on various types of Trojans, and all Trojans are successfully detected with 0 false positive and negative rates in less than 14 s in the worst case.