IEEE transactions on very large scale integration (VLSI) systems

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

INTERSUBBAND RELAXATION IN GaAs/Al x Ga 1-x As QUANTUM WELL STRUCTURES

Two concentration ranges of silicon doping in MBE-grown GaAs films have been investigated in some detail. In lightly doped films, with a free-electron concentration of ≈1016cm−3, low-temperature photoluminescence spectra have been analysed to develop a model to account for spectral features previously attributed to Ge and Si acceptor levels. In heavily doped films, a maximum free-electron concentration of ≈7×1018 cm−3 has been obtained, which is only rather weakly dependent on growth conditions and the nature of the arsenic species (As2 or As4). Transmission electron microscopy has shown that no significant precipitation effects occur when higher Si fluxes are used but there is evidence for autocompensation. The maximum PL intensity (300 K) is found at a lower free electron concentration then with Sn-doped films, and is more sharply peaked, but there is no evidence for an anomalous Moss-Burstein shift.

Silicon doping of MBE-grown GaAs films

Physics of Semiconductor Devices. S. M. Sze. Interscience (Wiley), New York, 1969. xvi + 814 pp., illus. $19.95

The velocity‐field characteristics of hot electrons moving one dimensionally in the lowest subband of a polar semiconductor quantum‐well wire are obtained on a drifted Maxwellian model and also by the Monte Carlo technique. No negative differential resistance is obtained in contradiction to a previous prediction. The size effects at low temperatures are found to be more significant in the drifted Maxwellian model. Our calculations show that the one‐dimensional (1‐D) mobility for large transverse widths may be higher than the 3‐D mobility.

One‐dimensional hot‐electron transport in quantum‐well wires of polar semiconductors

This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multiplexers. Full adder is a very common example of combinational circuits and is used widely in Application Specific Integrated Circuits (ASICs). It is always advantageous to have low power action for the sub components used in VLSI chips. The explored technique of realization achieves a low power high speed design for a widely used subcomponent-full adder. Simulated outcome using state-of-art simulation tool shows finer behavioral performance of the projected method over general CMOS based full adder. Power, speed and area comparison between conventional and proposed full adder is also presented.

Design & study of a low power high speed full adder using GDI multiplexer

An experiment was conducted to observe the efficacy of some neonicotinoidsagainst aphid of okra during pre- kharif season of 2010 and 2011 at Instructional Farm , Bidhan Chandra Krishi Viswavidyalaya. Imidacloprid 17.8 SL@ 50 g a.i. ha -1 was found as a most effective neonicotinoid insecticide against aphid. It recorded least aphid infestation and 84.54 % reduction of population over control. To control aphid populationof okra the other two neonicotinoidsviz., thiamethoxam25WG @ 50 g a.i. ha -1 and acetamiprid 20SP @ 40 g a.i. ha -1 were also found at par with imidacloprid and showed better result than acephate 75WP and dimethoate 30EC. Considering incremental cost ben efit ratio acetamiprid 20SP @ 40g a.i. ha -1 was found most economic over other neonicotinoids . None of the neonicotinoids haveadverse effect on natural enemies of aphid in okra ecosystem.

/pdf/bio-efficacy-of-neonicotinoids-against-aphis-gossypii-glover-36golwrfsp.pdf

Bio-efficacy of neonicotinoids against Aphis gossypii Glover of okra.

The richer variety of Klein–Gordon basis is already established for discrete breathers in metamatetrials. Based on this attempt, we show various anomalous Fano resonance behaviors that have been experimentally observed, but cannot be explained by nonlinear Schrodinger model. Certain material parameters of Klein–Gordon lattice in metamaterials are related for the first time with characteristics of Fano resonance, which can be utilized for beam filtering and for high-resolution biological sensing technology. Although relations with coupling and other parameters exist, the most remarkable relation is observed with linear permittivity that could control the wave transmission characteristics in metamaterials for applications in optical engineering.

Fano resonance due to discrete breather in nonlinear Klein–Gordon lattice in metamaterials

This paper represents a new design of a low power, low latency Wallace tree multiplier. Wallace Tree algorithm is one of the most commonly used operations in modern days DSP applications as it can provide a fast and area efficient strategy for higher operand multiplication. For higher bits of multiplications the addition operation of partial products includes greater delay and complexity. In this present communication a number of techniques are applied in the partial products addition circuitry to optimize the area delay and speed of the Wallace multiplier. Proposed Design is synthesized for $4\mathrm{x}4$ bit multiplication using standard CAD tool design compiler in 250nm process technology. Simulation results show that the proposed multiplier design has the best power and delay results as compared to other available multipliers.

Aniruddha Ghosal

Papers

One‐dimensional hot‐electron transport in quantum‐well wires of polar semiconductors

Design & study of a low power high speed full adder using GDI multiplexer

Bio-efficacy of neonicotinoids against Aphis gossypii Glover of okra.

Fano resonance due to discrete breather in nonlinear Klein–Gordon lattice in metamaterials

Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique for On-chip Digital Filter Applications