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Aniruddha Ghosal

Bio: Aniruddha Ghosal is an academic researcher from University of Calcutta. The author has contributed to research in topics: Electron mobility & Scattering. The author has an hindex of 7, co-authored 42 publications receiving 161 citations.

Papers
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Proceedings ArticleDOI
26 Nov 2022
TL;DR: In this paper , a CMOS comparator has been designed using 180 nm technology node to minimize the power consumption and reduce the offset voltage of the comparator block, which can also be used for detectors requiring high sensitivity.
Abstract: In this research paper, a CMOS comparator has been designed using 180 nm technology node. The purpose of this design is to minimize the power consumption and reduce the offset voltage of the comparator block. An Analog to Digital Converter (ADC) designed with this designed comparator will be compatible with low-power applications and provide good resolution. The proposed comparator can also be used for detectors requiring high sensitivity.
Journal ArticleDOI
TL;DR: In this paper, a new technique has been introduced for implementing low power area efficient sub-threshold voltage level shifter (LS) circuit, which consists of on-line level shifters.
Abstract: In the present communication, a new technique has been introduced for implementing low-power area efficient sub-threshold voltage level shifter (LS) circuit. The proposed LS circuit consists of onl...
Book ChapterDOI
01 Jan 2019
TL;DR: In this article, the behavior of gallium nitride transistor under the electric-optical phonon scattering is studied and the variation of current density with the concentration charge density is explained.
Abstract: The behavior of gallium nitride transistor under the electric–optical phonon scattering is studied and the variation of current density with the concentration charge density is explained. Due to polarization in GaN, two-dimensional electron gas causes the electrons drift velocity to change when some voltage applied to device. The mobility of GaN MOSFET is been studied and plotted with respect to the temperature. The current density which is related to the drift velocity and carrier concentration is analyzed and plotted.

Cited by
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Journal ArticleDOI
TL;DR: A comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics, including a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics.
Abstract: Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

189 citations

Journal ArticleDOI
J.H. Neave1, P.J. Dobson1, J.J. Harris1, Philip Dawson1, B.A. Joyce1 
TL;DR: In this article, two concentration ranges of silicon doping in MBE-grown GaAs films have been investigated in some detail, and the maximum free-electron concentration of ≈7×1018 cm−3 has been obtained, which is only rather weakly dependent on growth conditions and the nature of the arsenic species.
Abstract: Two concentration ranges of silicon doping in MBE-grown GaAs films have been investigated in some detail. In lightly doped films, with a free-electron concentration of ≈1016cm−3, low-temperature photoluminescence spectra have been analysed to develop a model to account for spectral features previously attributed to Ge and Si acceptor levels. In heavily doped films, a maximum free-electron concentration of ≈7×1018 cm−3 has been obtained, which is only rather weakly dependent on growth conditions and the nature of the arsenic species (As2 or As4). Transmission electron microscopy has shown that no significant precipitation effects occur when higher Si fluxes are used but there is evidence for autocompensation. The maximum PL intensity (300 K) is found at a lower free electron concentration then with Sn-doped films, and is more sharply peaked, but there is no evidence for an anomalous Moss-Burstein shift.

75 citations