Annalisa Cappellani

TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.

TL;DR: In this paper, the authors presented the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) and showed that the JAM devices showed better channel mobility and lower gate capacitance than the IM control counterparts at matched Ioff.

TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.

TL;DR: In this article, a method for making a semiconductor device is described, which comprises forming a first dielectric layer on a substrate, a trench within the first layer, and a second layer on the substrate.

TL;DR: In this article, gate contact structures over active portions of gates and methods of forming such gate contact structure are described, where the source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active regions.