A
Anoop Gupta
Researcher at Stanford University
Publications - 66
Citations - 13501
Anoop Gupta is an academic researcher from Stanford University. The author has contributed to research in topics: Cache & Shared memory. The author has an hindex of 39, co-authored 66 publications receiving 13362 citations.
Papers
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Proceedings ArticleDOI
The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Book
Parallel Computer Architecture: A Hardware/Software Approach
TL;DR: This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures and provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.
Proceedings ArticleDOI
Memory consistency and event ordering in scalable shared-memory multiprocessors
Kourosh Gharachorloo,Daniel E. Lenoski,James Laudon,Phillip B. Gibbons,Anoop Gupta,John L. Hennessy +5 more
TL;DR: A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced and is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization.
Journal ArticleDOI
SPLASH: Stanford parallel applications for shared-memory
TL;DR: This work presents the Stanford Parallel Applications for Shared-Memory (SPLASH), a set of parallel applications for use in the design and evaluation of shared-memory multiprocessing systems, and describes the applications currently in the suite in detail.
Journal ArticleDOI
The directory-based cache coherence protocol for the DASH multiprocessor
TL;DR: The design of the DASH coherence protocol is presented and how it addresses the issues of correctness, performance and protocol complexity are discussed and compared to the IEEE Scalable Coherent Interface protocol.