Anshul Gupta

Bio: Anshul Gupta is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Drain-induced barrier lowering & Subthreshold slope. The author has an hindex of 5, co-authored 20 publications receiving 76 citations.

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Abstract: Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

Abstract: A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented The impact of high-frequency AC stress bias on self-heating (SH) enhanced hot-carrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias The influence of SH on electrical parameter degradation due to hot-carriers is shown as an important metric for accurate device reliability analysis The relative contribution of bulk and interface traps is determined to identify the dominant mechanism responsible for HCD for different device geometries The device behavior is thoroughly studied under hot-carrier DC and AC stresses for different device design parameters, such as effective oxide thickness, number of fins, and channel length Based on measured data, we have proposed an empirical model for reliability degradation, which takes into account some of the key device design parameters and stress bias frequency

Investigation of Hot-Carrier Degradation in 0.18- $\mu$ m MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

Abstract: In this work, we investigate the hot-carrier reliability in $0.18{\mu}\text{m}$ MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs = Vds/2 and maximum hot-electron injection condition Vgs = Vds . Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.

Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs

Abstract: An analytical model of parasitic capacitance in inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness ( ${T}_{\textsf {iox}}$ ) and inserted-oxide recess ( ${T}_{\textsf {rec}}$ ), is shown using the proposed model and TCAD simulations.

A Device-to-System Perspective Regarding Self-Heating Enhanced Hot Carrier Degradation in Modern Field-Effect Transistors: A Topical Review

Abstract: As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important concern for device performance, output power density, run-time variability, and reliability of modern field-effect transistors. The self-heating effect is aggravated as the device footprint scales down for higher level of integration (low-power devices) or as the devices are operated in ultrahigh voltage regimes (high-power devices). In this article, we focus on the implications of self-heating on hot carrier degradation (HCD) of modern transistors by integrating within a coherent theoretical framework a broad range of experimental data scattered in the literature. We explain why system integration exacerbates transistor self-heating, while high-frequency digital operation ameliorates it, suggesting an opportunity for co-optimization. We conclude this article by discussing the various material–device–system design strategies to reduce HCD and suggesting open problems for further research.

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

A Vertical Combo Spacer to Optimize Electrothermal Characteristics of 7-nm Nanosheet Gate-All-Around Transistor

Abstract: In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA) transistor with a vertical combo spacer and different underlap/overlap channels is studied by the 3-D TCAD simulation. To achieve high authoritative evidences, the ${I}_{\text {d}}$ – ${V}_{\text {g}}$ characteristic with SHE is calibrated with the experimental data. First, the change of electrical characteristic introduced by different dielectrics of a single- ${k}$ spacer is investigated, and the results show that the current of ON-state ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is a power function of relative permittivity, whereas the OFF-state ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) exhibits a linear dependence. Second, a novel vertically wrapped combo spacer is proposed to achieve a compromise between thermal characteristic and electrical performance for the first time. The electrothermal characteristics of the combo spacer under different underlap/overlap channels are also studied, and the results showed that the combo spacer composed of inner Si3N4 and outer HfO2 has the highest ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ but smaller thermal resistance and lower lattice temperature compared with other different combinations. At last, a CMOS inverter with Si3N4/HfO2 combo spacer is demonstrated for its improvement in propagation delay.