Polish National Science Centre under the grants number N N516 475440, N N516 481840 and by the Polish Ministry of Science and Higher Education under the grant number N N519 442339

Introduction to models of quantum computation and quantum programming languages

Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.

Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs

Reversible logic gates, which are proven to provide zero power dissipation under ideal conditions, are in high demand for future computing technologies. Using reversible logic gates, this study provides an improved design for a low-cost 4 × 4 multiplier circuit module. The module can implement 8 × 8, 16 × 16 and up higher order multiplier circuits. In terms of gate counts, garbage outputs, constant inputs, and quantum cost, the suggested multiplier circuit using minimum number of half adders and full adders excels existing designs. Moreover, this concept can be used to implement different complex systems in the field of nanotechnology. The RTL design of the suggested multiplier circuit is then shown, followed by a simulation waveform that illustrates how the design works. The Xilinx ISE 14.7 software tool is also used to evaluate experimental results based on the on-chip power, delay, and other relevant parameters. 

An Optimized Low-Cost 4 × 4 Multiplier Circuit Design Using Reversible Logic Gates

There is an ever increasing demand for low-power and high-speed designs due to the emergence of portable, handheld gadgets which run on batteries. More and more research works in VLSI are concentrated on different methodologies to reduce the power consumption of a system and also increase its throughput. Multiplication is an important operation in almost all computations. Design of multipliers with low power utilization and increased throughput will lead to systems with reduced power usage and high speed. Vedic Multipliers based on the Urdhava Tiryakbhyam sutra delivers results faster than the customary methods. Reversible logic gates when used in a circuit lead to little or no power dissipation. The paper proposes a system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power. The designed system is optimized by combining the low power strategy of reversible logic and the high speed calculation of Urdhava Tiryakbhyam Vedic multiplier.

Ansiya Eshack

Papers

Speed and Power Efficient Reversible Logic Based Vedic Multiplier