Anthony J. Lochtefeld

Bio: Anthony J. Lochtefeld is an academic researcher from TSMC. The author has contributed to research in topics: Layer (electronics) & Substrate (electronics). The author has an hindex of 32, co-authored 64 publications receiving 4983 citations. Previous affiliations of Anthony J. Lochtefeld include Massachusetts Institute of Technology.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

High quality Ge on Si by epitaxial necking

Abstract: We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.

Fundamentals of Modern VLSI Devices

Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

High-performance Ge-on-Si photodetectors

Abstract: The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

Tuning charge transport in solution-sheared organic semiconductors using lattice strain

Abstract: A solution-processing method known as solution shearing is used to introduce lattice strain to organic semiconductors, thus improving charge carrier mobility. Solution-processed organic semiconductors show great promise for application in cheap and flexible electronic devices, but generally suffer from greatly reduced electronic performance — most notably charge-carrier mobilities — compared with their inorganic counterparts. Borrowing a trick from the inorganic semiconductor community, Giri et al. show how the introduction of strain into an organic semiconductor, through a simple solution-processing technique, modifies the molecular packing within the material and hence its electronic performance. For one material studied, the preparation of a strained structure is shown to more than double the charge-carrier mobility. Circuits based on organic semiconductors are being actively explored for flexible, transparent and low-cost electronic applications1,2,3,4,5. But to realize such applications, the charge carrier mobilities of solution-processed organic semiconductors must be improved. For inorganic semiconductors, a general method of increasing charge carrier mobility is to introduce strain within the crystal lattice6. Here we describe a solution-processing technique for organic semiconductors in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules. For organic semiconductors, the spacing between cofacially stacked, conjugated backbones (the π–π stacking distance) greatly influences electron orbital overlap and therefore mobility7. Using our method to incrementally introduce lattice strain, we alter the π–π stacking distance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) from 3.33 A to 3.08 A. We believe that 3.08 A is the shortest π–π stacking distance that has been achieved in an organic semiconductor crystal lattice (although a π–π distance of 3.04 A has been achieved through intramolecular bonding8,9,10). The positive charge carrier (hole) mobility in TIPS-pentacene transistors increased from 0.8 cm2 V−1 s−1 for unstrained films to a high mobility of 4.6 cm2 V−1 s−1 for a strained film. Using solution processing to modify molecular packing through lattice strain should aid the development of high-performance, low-cost organic semiconducting devices.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...