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Antonis Paschalis
Researcher at National and Kapodistrian University of Athens
Publications - 114
Citations - 2212
Antonis Paschalis is an academic researcher from National and Kapodistrian University of Athens. The author has contributed to research in topics: Fault coverage & Fault model. The author has an hindex of 27, co-authored 112 publications receiving 2130 citations. Previous affiliations of Antonis Paschalis include Nuclear Regulatory Commission & Athens State University.
Papers
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Journal ArticleDOI
Software-based self-testing of embedded processors
TL;DR: This paper presents a high-level, functional component-oriented, software-based self-testing methodology for embedded processors and validate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture.
Journal ArticleDOI
Effective software-based self-test strategies for on-line periodic testing of embedded processors
TL;DR: A new SBST methodology with a new classification and test-priority scheme for processor components is introduced and the self-test routine code styles for the three more effective test pattern generation (TPG) strategies are analyzed in order to select the most effective self- test routine for on-line periodic testing of a component under test.
Journal ArticleDOI
Systematic Software-Based Self-Test for Pipelined Processors
Dimitris Gizopoulos,Mihalis Psarakis,M. Hatzimihail,Michail Maniatakos,Antonis Paschalis,Anand Raghunathan,Srivaths Ravi +6 more
TL;DR: A systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic, and applies it to two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model.
Proceedings ArticleDOI
Systematic software-based self-test for pipelined processors
Mihalis Psarakis,Dimitris Gizopoulos,Miltiadis Hatzimihail,Antonis Paschalis,Anand Raghunathan,Srivaths Ravi +5 more
TL;DR: A systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic, and applies it to two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model.
Proceedings ArticleDOI
Effective software-based self-test strategies for on-line periodic testing of embedded processors
TL;DR: This paper introduces a new SBST methodology with a new classification scheme for processor components and analyzes the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self- test routine for on-line periodic testing of a component under test.