Anurag Verma

Bio: Anurag Verma is an academic researcher from VIT University. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

Design of Multi-Segment Hybrid Type Content Addressable Memory in High Performance FinFET Technology

Abstract: Power dissipation due to memories has become a major concern of modern digital design. Scaling of CMOS technology has lead to short channel effects. Here CAM cells are designed using FinFET which have better gate control over drain to source current. The CAM cells designed with 30nm LG are used in multi-segment hybrid CAM architecture. The results are compared with the original hybrid CAM. It is observed that the energy metric of proposed architecture is 7% less compared to hybrid CAM.

VLSI Design and Implementation of Low Power PBCAM: A Tutorial and Survey

Abstract: Background: A CAM is a fully parallel operating device. For high speed data searching functions CAM provides very efficient hardware architecture1. Statistical Analysis: This paper presents novel developments in the recent design of high capacity Content Addressable Memory (CAM) and Pre-computational Based CAM (PB-CAM). A graphical analysis has been shown between PB-CAM using static parameter circuit and proposed parameter circuit for power, delay and power-delay product in 90nm CMOS technology. Findings: There are many techniques made for designing a CAM by taking in mind to get lowpower, low-noise, high-speed, less hardware cost and less data comparisons and with minimum number of transistors and gates. There are, Traditional Dynamic CAM architecture, Ones-Count PB-CAM, Parity function PB-CAM, Remainder function PB-CAM, Block-XOR PB-CAM and Master–Slave Match Line (MSML) design. In this paper we have compared 9T and 7T CAM cell operations. Static parameter circuit is compared with proposed parameter comparison circuit for powerdelay product in 45nm CMOS technology. Applications: CAM function can be used in broader applications, such as data compression, LAN bridges, data comparison, switches, Lookup tables, Asynchronous Transfer Mode (ATM) switches, databases, communication devices, communication networks, tag directories and high speed Ethernet etc.

Low Power and High Speed PB-CAM with XNOR-NAND Parameter Comparison Circuit

Abstract: Objectives: Low power consumption, high-speed and low-cost are the major important needs in several applications like Asynchronous Transfer Mode (ATM) and Giga-bit Ethernet networks To achieve high-speed parallel data comparisons in internet routers PB-CAM is the one of best hardware approaches In the present work, PB-CAM is modified for improving performance of CAM architecture Methods/Statistical Analysis: In PB-CAM unit the main building blocks of the process is parameter extractor, parameter comparison circuit and CAM cell The PB-CAM is faster and low-power consumption than the traditional CAM The PB-CAM unit implemented by 180nm, 90nm and 45nm CMOS technology in Cadence The parameter-extractor and static-parameter-comparison circuits implemented in 180nm, 90nm and 45nm CMOS technology Findings: The power consumption of the proposed Parameter-Comparison circuit using XNOR-NAND CMOS logic is 002135uW at a supply voltage of 045V in 45nm CMOS technology for a 4x4 (4-bits of stored parameter-extracted data and 4-bits of input parameter-extracted data) size parameter comparison data at 10-30MHz For 15-bit input data, the PB-CAM with proposed parameter comparison circuit is consuming an average power of 1291uW at a supply of 09V and a frequency of 10-30MHz The results show that the PB-CAM unit using proposed parameter comparison circuit is faster, low-power consumption and low-cost than the PB-CAM with static parameter comparison circuit Application/Improvements: PB-CAM circuit used in high-speed look-up-tables (LUTs), ATMs, routers and etc In future, further advancements can be done in PB-CAM unit by combining different techniques such as match-line-sense-amplifier, ones-count, block-XOR, parity-bit to achieve low-power, low-cost and high-speed search and read operations in network routers