Apolinar Crespo

Bio: Apolinar Crespo is an academic researcher from Wright-Patterson Air Force Base. The author has contributed to research in topics: High-electron-mobility transistor & Biasing. The author has an hindex of 1, co-authored 1 publications receiving 96 citations.

Electrothermal Simulation and Thermal Performance Study of GaN Vertical and Lateral Power Transistors

Abstract: In this paper, we present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and compare their thermal performance. The models are first validated by comparison with experimental dc characteristics, and then used to study the maximum achievable power density of the device without the peak temperature exceeding a safe operation limit of 150°C (P150°C). It is found that the vertical MOSFETs have the potential to achieve a higher P150°C than the lateral HEMTs, especially for higher breakdown voltages and higher scaling level designs.

Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs

Abstract: High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.

A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

Abstract: We review the Raman thermography technique, which has been developed to determine the temperature in and around the active area of semiconductor devices with submicron spatial and nanosecond temporal resolution. This is critical for the qualification of device technology, including for accelerated lifetime reliability testing and device design optimization. Its practical use is illustrated for GaN and GaAs-based high electron mobility transistors and opto-electronic devices. We also discuss how Raman thermography is used to validate device thermal models, as well as determining the thermal conductivity of materials relevant for electronic and opto-electronic devices.

Channel Temperature Analysis of GaN HEMTs With Nonlinear Thermal Conductivity

Abstract: This paper presents an enhanced, closed-form expression for the thermal resistance, and thus, the channel temperature of AlGaN/gallium nitride (GaN) HEMTs, including the effect of the temperature-dependent thermal conductivity of GaN and SiC or Si substrates. In addition, the expression accounts for temperature increase across the die-attach. The model’s validity is verified by comparing it with experimental observations. The model results also compare favorably with those from finite-element numerical simulations across the various device geometric and material parameters. The model provides a more accurate channel temperature than that from a constant thermal conductivity assumption; this is particularly significant for GaN/Si HEMTs where the temperature rise is higher than in GaN/SiC. The model is especially useful for device and monolithic microwave integrated circuit designers in the thermal assessment of their device design iterations against required performance for their specific applications.

Device-Level Thermal Management of Gallium Oxide Field-Effect Transistors

Abstract: The ultrawide bandgap (UWBG) (~4.8 eV) and melt-grown substrate availability of $\beta $ -Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers’ attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of ~1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.