Arpan Chakrabarty

Bio: Arpan Chakrabarty is an academic researcher from University of Calcutta. The author has contributed to research in topics: Electronic design automation & Biochip. The author has an hindex of 3, co-authored 6 publications receiving 13 citations.

A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area

Abstract: The guard zone computation problem finds vast applications in the field of VLSI physical design automation and design of embedded systems, where one of the major purposes is to find an optimized way to place a set of 2D blocks on a chip floor. In VLSI layout design, the circuit components (or the functional units/modules or groups/blocks of different subcircuits) are not supposed to be placed much closer to each other in order to avoid electrical (parasitic) effects among them (http://en.wikipedia.org/wiki/Curve_orientation, [13]). The (group of) circuit components on a chip floor may be viewed as a set of polygonal regions on a two-dimensional plane. Each (group of) circuit component(s) C i is associated with a parameter δ i such that a minimum clearance zone of width δ i is to be maintained around C i . The regions representing the (groups of) circuit components are in general isothetic polygons, but may not always be limited to convex ones. The location of the guard zone (of specified width) for a simple polygon is a very important problem for resizing the (group of) circuit components. In this paper, we have developed an algorithm to compute the guard zone of a simple polygon as well as to exclude the overlapped regions among the guard zones, if any. If the number of vertices in the given polygon is n, then our algorithm requires O(n log n + I log n) time, where I is the number of intersections among the guard zones. So, it is output sensitive in nature that depends on the value of δ i . The algorithm developed in the paper is proved to report a preferred guard zone of the given simple polygon excluding all the intersections, if any.

An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics

Abstract: Digital Microfluidic Biochips (DMFB) is revolutionizing many areas of Microelectronics, Biochemistry, and Biomedical sciences. It is also known as 'Lab-on-a-Chip' for its popularity as an alternative for laboratory experiments. Pin count reduction and cross contamination avoidance are some of the core design issues for practical applications. Nowadays, due to emergency and cost effectiveness, more than one assay operations are required to be performed simultaneously. So, parallelism is a necessity in DMFB. Having an area of a given chip as a constraint, how efficiently we can use a restricted sized biochip and how much parallelism can be incorporated are the objectives of this paper. The paper presents a design automation flow that augments parallelism in applications considering cross contamination problem as well.

An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance

Abstract: These days, in emergency, multiple assay operations are required to be performed at parallel Area of a given chip as a constraint, how efficiently we can use the chip and how much parallelism can be built-in are the objectives of this paper A typical application of an assay may characterize a sample where, say only one type of reagent and multiple samples have been considered, or vice versa, and identify some factor(s) of the sample(s) under requirement in parallel A generalized application may also consider more samples and more reagents for respective findings at parallel In our experimentation, we effectively do this task in parallel for five such sets of sub regions of a given restricted sized chip in Digital microfluidics using an array based partitioning pin assignment technique, where cross contamination problem has also been considered, and efficiency of proper taxonomy of a given sample has also been improved

A New Move Toward Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics

Abstract: Digital microfluidic biochip (DMFB) is modernizing many areas of Microelectronics, Biochemistry, and Biomedical sciences. As a substitute for laboratory experiments, it is also widely known as ‘lab-on-a-chip’ (LOC). Minimization in pin count and avoiding cross-contamination are some of the important design issues for realistic relevance. These days, due to urgent situation and cost efficacy, more than one assay operations are essential to be carried out at the same time. So, parallelism is inevitable in DMFB. Having an area of a given chip as a constraint, how efficiently we can use a limited sized chip and how much parallelism can be incorporated are the objectives of this paper. The paper presents a design automation flow that enhances parallelism by adopting Connect-5 structure of pin configuration and considering cross-contamination problem as well. The algorithm developed in this paper assumes array-based partitioning of modules as pin-constrained design technique, where a constant number of pins have been used for desired scheduling of reagent and sample droplets. To avoid cross-contamination and at the same time to minimize the delay required for washing, wash droplet scheduling and proper placement of modules to minimize wash operations are also taken care of.

A connect-5 structure based parallel assay operations in a restricted sized chip in digital microfluidics

Abstract: Digital Microfluidic Biochips (DMFB) is modernizing many areas of Microelectronics, Biochemistry, and Biomedical sciences. As an alternative for laboratory experiments it is popularly also known as `Lab-on-a-Chip'. Reduction in pin count and avoiding cross contamination are some of the important design issues for realistic relevance. These days, due to urgent situation and cost efficacy, more than one assay operations are essential to be carried out at the same time. So, parallelism is inevitable in DMFB. Having an area of a given chip as a constraint, how efficiently we can use a limited sized chip and how much parallelism can be incorporated are the objectives of this paper. The paper presents a design automation flow that enhances parallelism by adopting Connect-5 structure of pin configuration and considering cross contamination problem as well. The algorithm developed in this paper assumes array based partitioning of modules as pin constrained design technique, where a constant number of pins has been used for desired scheduling of reagent and sample droplets. To avoid cross contamination and at the same time to minimize the delay required for washing, wash droplet scheduling and proper placement of modules to minimize wash operations are also taken care of.

Development of advanced operators for enhanced on-chip biosensing in digital microfluidic platforms

Abstract: ................................................................................................................................... ii Preface ..................................................................................................................................... iii Table of

An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance

Abstract: These days, in emergency, multiple assay operations are required to be performed at parallel Area of a given chip as a constraint, how efficiently we can use the chip and how much parallelism can be built-in are the objectives of this paper A typical application of an assay may characterize a sample where, say only one type of reagent and multiple samples have been considered, or vice versa, and identify some factor(s) of the sample(s) under requirement in parallel A generalized application may also consider more samples and more reagents for respective findings at parallel In our experimentation, we effectively do this task in parallel for five such sets of sub regions of a given restricted sized chip in Digital microfluidics using an array based partitioning pin assignment technique, where cross contamination problem has also been considered, and efficiency of proper taxonomy of a given sample has also been improved

Multiple parallel assay operations with cross contamination avoidance in a given biochip

Abstract: Digital microfluidic biochips are reforming many areas of biochemistry, biomedical sciences, as well as microelectronics. It is renowned as lab-on-a-chip for its appreciation as a substitute for laboratory experiments. Nowadays, for emergency purposes and to ensure cost efficacy, multiple assay operations are essential to be carried out simultaneously. In this context, parallelism is of utmost importance in designing biochip while the size of a chip is a constraint. Hence, the objective of this study is to enhance the performance of a chip in terms of its throughput, electrode utilisation, and pin count as well. Here, the authors have considered some of the most familiar assay requirements where a sample is to be analysed using different reagents, and identify some parameter(s) of the sample(s) under consideration. Moreover, sample preparation is a vital task in digital microfluidic biochip; thus, dilution of different samples up to different concentrations using buffer (neutral) fluid is a crucial issue. In this design, the authors effectively perform this task in parallel in a number of sub-regions of a given restricted sized chip using an array based partitioning pin-assignment technique while taking care of the cross contamination problem. The design has been verified for some significant real life assay examples.

An innovative approach towards detection and exclusion of overlapped regions in guard zone computation

Abstract: The guard zone computation problem is of utmost importance in the domain of VLSI physical design automation as one of the major purposes is to find an optimized way to place a set of two-dimensional blocks on a chip floor. Beyond this, it has huge significance in the field of robotic motion planning, Geographical information system, automatic monitoring of metal cutting tools and design of any embedded systems. In VLSI layout design, the circuit components (or the functional units / modules or groups / blocks of different sub-circuits) that may be viewed as a set of polygonal regions on a two-dimensional plane, are not supposed to be placed much closer to each other in order to avoid electrical (parasitic) effects among them. Each (group of) circuit component(s) C i is associated with a parameter δ i such that a minimum clearance zone of width δ i is to be maintained around C i . If the guard zonal regions overlap, we have to remove the overlapped regions in order to compute the resultant outer guard zone (sometimes inner guard zones are also an issue to be considered). The location of guard zone (of specified width) for a simple polygon is a very important problem for resizing a (group of) circuit component. In this paper, we have developed an algorithm to compute the guard zone of a simple polygon as well as to exclude the overlapped regions among the guard zonal segments (if any) in O(nlogn) time, where « is the number of vertices of the given simple polygon.

A comprehensive approach towards guard zone computation detecting and excluding the overlapped regions

Abstract: The guard zone computation problem finds immense applications in the field of VLSI physical design automation and design of embedded systems, where one of the major purposes is to find an optimized way to place a set of two-dimensional blocks on a chip floor. In VLSI layout design, the circuit components (or the functional units / modules or groups / blocks of different sub-circuits) that may be viewed as a set of polygonal regions on a two-dimensional plane, are not supposed to be placed much closer to each other in order to avoid electrical (parasitic) effects among them [12]. Each (group of) circuit component(s) C i is associated with a parameter δ i such that a minimum clearance zone of width δ i is to be maintained around C i . If the guard zonal regions overlap, we have to remove the overlapped regions in order to compute the resultant outer guard zone (sometimes inner guard zones are also an issue to be considered). The location of the guard zone (of specified width) for a simple polygon is a very important problem for resizing the (group of) circuit components. In this paper, we have developed an algorithm to compute the guard zone of a simple polygon as well as to exclude the overlapped regions among the guard zonal segments (if any) in O(n log n) time, where n is the number of vertices of the given simple polygon.