Arun Kumar

Bio: Arun Kumar is an academic researcher from Indian Institute of Technology Patna. The author has contributed to research in topics: MOSFET & Subthreshold conduction. The author has an hindex of 7, co-authored 25 publications receiving 144 citations. Previous affiliations of Arun Kumar include University of Tokyo.

A Threshold Voltage Model of Silicon-Nanotube-Based Ultrathin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects

Abstract: In this paper, a quantum-mechanical threshold voltage model for ultrathin double gate-all-around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's and 2-D Schrodinger's equations in the channel region. The parabolic potential approximation is considered for Poisson's equation solution, whereas a hollow cylindrical potential well in the channel region is assumed to solve Schrodinger's equation. Simple equations for the wave function and energy quantization in the channel of DGAA MOSFET have been formulated. Discretized energy levels have been used for channel charge calculation in subthreshold regime of device operation. The calculated channel charge is compared with a threshold charge to formulate the threshold voltage model. The effects of the device parameters such as the channel thickness, oxide thickness, doping, etc. on threshold voltage and DIBL have been extensively studied. The proposed model results have been verified by comparing with the numerical simulation results obtained from the 3-D device simulator Visual TCAD of Cogenda Int.

Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method

Abstract: Causes of drain current local variability are analyzed by decomposing into current variability components. Besides V TH and G m components, it is newly found that effects of “current onset” variability caused by channel potential fluctuations largely contribute to the current variability and that G m component is relatively small in the saturation region. It is shown that both V TH and current onset components decreases with reducing channel dopants, indicating that intrinsic channel is very effective to reduce current variability.

Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs

Abstract: Intrinsic channel SOI MOSFETs were fabricated and their variability were compared with conventional bulk MOSFETs. It is found for the first time that, besides V TH variability, both DIBL variabitlity and current-onset voltage variability are well suppressed in the intrinsic channel SOI MOSFETs thanks to non-intentionally doped channel. Reduction of channel doping is essential to reduce the characteristics variability in scaled FETs.

An Insight Into Self-Heating Effects and Its Implications on Hot Carrier Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA) MOSFETs

Abstract: Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

Abstract: Simulations of up to 10 000 fully depleted thin-body silicon-on-insulator MOSFETs show that the standard deviation of the threshold voltage cannot be adequately used as a sole metric of device variability in such transistors. This is due to a sharp departure from normality of the threshold voltage distribution, and an enhanced influence of the source/drain-dopant fluctuations on the on-current and short-channel effects of the fully depleted thin-body silicon-on-insulator transistors. Both aspects have great ramifications for statistical compact models and for low-power SRAM designs.

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Abstract: Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of the V-groove bottom, was as short as 3 nm, and the channel thickness was between 1 and 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation were obtained for both n-FETs and p-FETs when the thickness of both the channel and gate dielectric film thickness was reduced to 1 nm. The origin of the excellent electrostatic control is discussed on the basis of fringe capacitance and quantum confinement effects in a nanometer-scale ultrathin Si layer where band-gap expansion, dielectric constant reduction, and increase in the dopant activation energy become prominent. The electrical characteristics of the ultrashort channel JL-FETs were found to be very sensitive to device parameters such as the channel thickness and dopant concentration.

The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes

Abstract: In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.

Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm

Abstract: ON-current (Ion) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis Variation sources of Ion are successfully extracted as independent contributions of threshold voltage Vt, transconductance Gm, and parasitic resistance Rpara As well as Vt variability, Gm variation exhibits a linear relationship in the Pelgrom plot However, the Gm variation is not reduced with scaling the gate dielectric thickness unlike the Vt variation Perspective for 14-nm FinFETs represents that the Gm variation will be the dominant Ion variation source A solution to reduce the Gm variation for the FinFET is also proposed

Measuring threshold voltage variability of 10G transistors

Abstract: Threshold voltage (V TH ) variability of 10G (10 billion) transistors is measured using a special device-matrix-array test-element-group (DMA TEG) exclusively for ultra-fast V TH measurements. It is found that V TH variability in nFETs almost follows the normal distribution up to ±6σ, while pFETs have a clear “tail” in low V TH region. The origin of the non-normal distribution is analyzed by measuring transistors fabricated in two different fabs and by 3D device simulation.