Ashim Kumar Mahato

Bio: Ashim Kumar Mahato is an academic researcher from Assam University. The author has contributed to research in topics: Very-large-scale integration & Destination-Sequenced Distance Vector routing. The author has an hindex of 2, co-authored 5 publications receiving 7 citations.

Via Minimization for Multi-layer Channel Routing in VLSI Design

Abstract: It is known that via minimization is a very important problem in multilayer channel routing. The main objective of via minimization is to improve the circuit performance and productivity, to reduce the completion rate of routing and also fabricate integrated circuit correctly. In this paper, we study on some important via minimization algorithms. Firstly we analyze via minimization problem in two-layer channel routing with movable terminals. In this assumption via minimization problem can be solve in polynomial time. Next we study a genetic algorithm for constrained via minimization. Next we observe how to minimize the number of vias using layout modification. The main significant of this method is to reduce the number of vias without increasing the routing area. Later we also study how via can be minimize in three layer channel routing. In this approach there is no any specific rule for layering and because of this result is better than earlier three layer channel routers. Lastly we analyze a heuristic algorithm to solve CVM problem for three layer channel routing. It is based on the breadth first search, there is no any restriction on layouts given as input and any wire segment can pass through without using via. Every heuristic algorithm constructs a graph model from a given layout. Lastly we have done one comparative study for all these algorithms and conclude this paper.

Architecture and implementation issues of multi-core processors and caching - a survey

Abstract: As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. This paper includes what brought about the change from single processor architecture to having multiple processors on a single die and some of the hurdles involved, and the technologies behind it. Having each processor on a single die allows much greater communication speeds between the processors. For multi-threading and multitasking, security and virtualization and physical restraints such as heat generation and die size, we need multi-core processor. Processor cache is the performance bottleneck in most current architectures. Next, we consider some of the issues involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of multi-processors.

A novel approach for constrained via minimization problem in VLSI channel routing

Abstract: Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.

A heuristic algorithm for via minimization in VLSI channel routing

Abstract: We know that via minimization is a very important problem in channel routing. The main aim of via minimization is to improve the circuit performance and productivity, to reduce the completion rate of routing and also to fabricate integrated circuit correctly. In this paper, we are using a heuristic algorithm for solving via minimization problem in VLSI channel routing with movable terminal. Here we concentrate on how fast we find out maximum independent set from the net intersection graph. That is why here we use heuristic technique to find the maximum independent set of a graph with polynomial time complexity. Next, we show how to use that maximum independent set to solve the via minimization problem using an example. Then, we show the experimental results and hardcopy solutions of some channel instances to prove the efficiency of this approach.

Using Probabilistic Optimization Algorithms to Reduce PAPR in OFDM System

Abstract: Orthogonal frequency division multiplexing (OFDM) is a swiftly growing multi-carrier modulation technique. OFDM gives high data rate for transmission of information from one location to another. Peak to average power ratio (PAPR) has been a constraining component of OFDM. Various techniques have been proposed to reduce PAPR. Partial Transmit Sequence (PTS) is a distortion less technique that improves PAPR performance. The PTS technique reduces PAPR by a fair margin. However, the major drawback of PTS is that for large number of IFFT calculations the computational complexity increases. Various optimization techniques have been implemented to reduce the complexity in PTS technique. In this paper, we propose an Ant Colony Optimization (ACO) based PTS technique to achieve least PAPR in OFDM. The simulation results confirm that the proposed technique can accomplish the noteworthy PAPR diminishment with less computational complexity.

An efficient approach to constrained via minimization for two-layer VLSI routing

Abstract: Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

Studies on the Impact of Cache Configuration on Multicore Processor

Abstract: The demand for a powerful memory subsystem is increasing with increase in the number of cores in a multicore processor. The technology adapted to meet the above demands are: increasing the cache size, increasing the number of levels of caches and bymeans of a powerful interconnection network. Caches feeds the processing element at a faster rate. They also provide high bandwidth local memory to work with. In this research, an attempt has beenmade to analyze the impact of cache size on performance of multicore processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN), also referenced from NIAGRA architecture. As the number of cores increases, traditional on-chip interconnect like bus and crossbar proves to be less efficient as well as suffers from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnects, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INoC) for multicore processors has been proposed. The benchmark results are presented using a full system simulator. Results shows that, using the proposed INoC,execution time can be significantly reduced, compared with MPIN.Cache size and set-associativity are the features on which the cache performance is dependent. If the cache size is doubled, then the cache performance can increase but at the cost of high hardware, larger area and more power consumption. Moreover, considering the small form-factor of themobile processors, increase in cache size affects the device size and battery running time. Re-organization and reanalysis of cache onfiguration ofmobile processors are required for achieving better cache performance, lower power consumption and chip area. With identical cache size, performance gained can be obtained from a novel cache mechanism. For simulation, we used SPLASH2 benchmark suite.

Study of Via Optimization Problem Based on Estimation of Distribution Algorithm

Abstract: Optimizing the number of vias is an important approach for improving the performance and the yield of printed circuit boards (PCBs). To optimize the vias of multilayer PCBs, first, we converted the circuit routing diagram into an undirected weighted topology. Then, the mathematical model of the via optimization problem was established on the basis of the topological weight segmentation method. Finally, it was solved using estimation of distribution algorithm (EDA). Compared with the traditional methods, the proposed method was intuitive and easy to implement with no invalid solution existing in the intermediate process and with high operation efficiency. The simulation experiments demonstrated that the proposed algorithm could effectively solve the via optimization problem, and EDA had faster convergence and better effectiveness than the genetic algorithm (GA).

A Comprehensive Survey on Strategies in Multicore Architectures, Design Considerations and Challenges

Abstract: CMOS technology in contemporary period is enhanced with advanced features and compatible storage system. Advanced CMOS technology provides functional density, increased performance, reduced power, etc. System-on-chip (SoC) technology provides a path for continual improvement in performance, power, cost, and size at the system level in contrast with the conventional CMOS scaling. When a single processor is transformed into multicore processor, it faces a lot of hazards to confine the circuits into single chip. To emphasize the importance of multicore architecture, this paper provides a comprehensive survey on multicore architectures designs, constraints, and practical issues.

A Survey on Heuristic Algorithms on Detailed Routing in Physical Design Automation

Abstract: Routing is one of the most complex stage in physical design. Detailed routing determines the exact place of tracks and via. The main objective ofdetailed routing is to reduce the area of an integrated chip . Minimization of wire length,number of tracks, channel length, congestion factor is the key problem in physical design. Routing is a process to interconnect all the nets within the channel considering all constraints(horizontal and vertical constraints) of that channel. Unlike traditional routing schemes ,all the traffic is along a single path, multipath routing scheme splitthe traffic among several paths in order to reduce the congestion. In this paper, we analyze different single-layer algorithms, two-layer algorithms and three layer algorithms and conclude that the objective of the routing problems like crosstalk, wire length, channel length, no of tracks and vias.