This work develops a thorough review of bioimpedance systems for healthcare applications. The basis and fundamentals of bioimpedance measurements are described covering issues ranging from the hardware diagrams to the configurations and designs of the electrodes and from the mathematical models that describe the frequency behavior of the bioimpedance to the sources of noise and artifacts. Bioimpedance applications such as body composition assessment, impedance cardiography (ICG), transthoracic impedance pneumography, electrical impedance tomography (EIT), and skin conductance are described and analyzed. A breakdown of recent advances and future challenges of bioimpedance is also performed, addressing topics such as transducers for biosensors and Lab-on-Chip technology, measurements in implantable systems, characterization of new parameters and substances, and novel bioimpedance applications.

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Fundamentals, Recent Advances, and Future Challenges in Bioimpedance Devices for Healthcare Applications

Introduction to circuit synthesis and design

In this study, a simple memristor circuit using only one Voltage Differencing Current Conveyor (VDCC), two PMOS transistors and one grounded capacitor, is designed. The presented memristor exhibits electronically controllable characteristics, which are superior to its counterparts. Both the memductance value and the operating frequency can be electronically tuned through voltage sources. The proposed memristor, which occupies 42.2 µm × 27.5 µm area excluding the area of the capacitor, is laid by using Cadence Environment using TSMC 0.18 µm process parameters. In addition, the proposed memristor is implemented by using discrete circuit elements on the breadboard and detailed analyses are given by changing the values of the discrete circuit elements. All results are compatible with the previous studies.

Electronically tunable memristor based on VDCC

In this paper, a new 2-dimensional chaotic map with a simple algebraic form is proposed. And the numerical solution of the corresponding fractional-order map is derived. It is novel that the new map still exhibits chaotic behaviors when the new map is expanded to fractional-order and improper fractional-order. The dynamical characteristics of these three forms are detected through the bifurcation diagram, the maximum Lyapunov exponent spectrum, Kolmogorov entropy and attractor portraits. More interestingly, the new map has multiple coexisting attractors, but the multistability of the fractional-order and improper fractional-order is more complicated than the integer-order form. In addition, the Permutation entropy (PE) complexity algorithm and 2-dimensional maximum Lyapunov exponent diagram are used to explore the dynamic changes of three forms when the amplitude changes simultaneously. The analysis shows that under the appropriate order, the chaotic range of the fractional-order and improper fractional-order is larger than that of the integer order. This research provides guidance on the application and teaching of discrete fractional-order systems.

Dynamic analysis of a new two-dimensional map in three forms: integer-order, fractional-order and improper fractional-order

New grounded and floating memristor emulators using OTA and CDBA

This research paper reports on a floating memristor model with minimum metal–oxide–semiconductor field-effect transistor count. The proposed structure uses only three nMOS transistors with a constant current bias and a single external capacitor. It offers less design complexity as compared to other existing memristor designs. The heart of the proposed design incorporates a MOS-based feedback circuit as an electronically controlled element for the memristance value. The memristor model has been integrated with 0.18- $\mu \text{m}$ Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) CMOS parameter. The pinched hysteresis loop of memristor for different frequency ranges and their composite characteristics are well analyzed using PSPICE simulation. The operating frequency range of the reported memristor is suitable up to few megahertz range. In addition to that application of the proposed MOS-memristor model is well described that comprises a Op-Amp-based Schmitt trigger circuit, a high-frequency modulation scheme, and an associative learning process. Finally, the postlayout simulation and experimental results are presented to validate the workability of the proposed memristor model.

A Simple Floating MOS-Memristor for High-Frequency Applications

This research article comes with a grounded as well as floating meminductor using voltage difference transconductance amplifier (VDTA). The proposed meminductor models have only two active VDTA and grounded capacitors each. The performance evaluation of the proposed meminductor is verified using post-layout simulation in the Cadence Virtuoso tool and experimentally using off the self component such as operational transconductance amplifier (OTA) for the implementation of VDTA with passive components. Moreover, neuromorphic circuit implementation as an application of the proposed meminductor is well incorporated in this literature.

High Frequency Meminductor Emulator Employing VDTA and its Application

This research article offers a floating memristor model using single voltage difference transconductance amplifier (VDTA) and grounded passive components. The proper utilization of VDTA port characteristics with passive components exhibits both incremental and decremental modes of operation without multiplier circuit. The performance analysis of proposed memristor is verified by using post layout Cadence Virtuoso simulation to examine the characteristics of all possible temperature and process Corners. In addition, experimental verification of VDTA-based memristor is done using commercially available operational transconductance amplifier (OTA) as IC CA3080. The results obtained through simulation and experiment follows the theoretical aspects. Moreover, an application perspective of the proposed design includes a brief neuromorphic circuit implementation for Pavlovian associative learning experiment.

Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation

This article presents a new chaotic and hyperchaotic oscillator with a sine-hyperbolic nonlinearity term. The proposed 3D chaotic system generates chaotic flow within an unstable node equilibrium. In addition, an extension of the proposed chaotic circuit produces 4D hyperchaotic nature by including an external capacitor in the basic design. This hyperchaotic system generates chaotic flow with the line of equilibrium which has an unstable null equilibrium termed as a special case of multi-stability. The chaotic behavior of the proposed system is obtained by using essential dynamical properties and its practical feasibility can be demonstrated through Current Feedback Operational Amplifier (CFOA) with traditional electronic components. The proposed chaotic and hyperchaotic system have some important features namely simple model without multiplication terms, simple circuitry, multi-stability, minimum component count and sensitive with passive components that signifies the advantages for the signal processing circuit and its applications. On the other hand, various bifurcation sequences along with its typical time series chaotic responses are well observed through simulation and experimental verification that validates the proposed chaotic oscillator theory.

New simple chaotic and hyperchaotic system with an unstable node

This research article introduces generalized design procedure for incremental/decremental memcapacitor using analog active device that brings a charge controlled floating memcapacitor emulator. The demonstration of generalized model using Dual X current conveyor differential input transconductance amplifier (DXCCDITA) as an analog active device comes with grounded capacitor and single resistor. The important features of proposed memcapacitor emulator in comparison with other emulators are the absence of mutator and multiplier circuits that causes less design complexity, CMOS compatible circuits, high frequency operation and few more. The switching operation incorporated in proposed memcapacitor model provides incremental and decremental mode of operation to control the state of memcapacitor for real time application. The CMOS implementation of DXCCDITA uses 0.18 µm CMOS technology parameter for the design verification. The performance of the memcapacitor is verified using PSPICE simulation and the observation validates the synchronization of theoretical perspective. An adaptive learning circuit is examined as an application with the proposed memcapacitor model that validates the usage of proposed model.

Ashish Ranjan

Papers

A Simple Floating MOS-Memristor for High-Frequency Applications

High Frequency Meminductor Emulator Employing VDTA and its Application

Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation

New simple chaotic and hyperchaotic system with an unstable node

Simple charge controlled floating memcapacitor emulator using DXCCDITA