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Ashutosh Gupta

Bio: Ashutosh Gupta is an academic researcher from Amity University. The author has contributed to research in topics: Field-programmable gate array & ModelSim. The author has an hindex of 8, co-authored 64 publications receiving 280 citations. Previous affiliations of Ashutosh Gupta include Guru Gobind Singh Indraprastha University & Central Electronics Engineering Research Institute.


Papers
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Proceedings ArticleDOI
27 Oct 2009
TL;DR: An algorithm for optimizing the Principal Component Analysis in gesture recognition is proposed, which makes use of covariance between factors to reduce data dimensions and provides a roadmap for how to reduce a complex data set to a lower dimension to reveal the sometimes hidden, simplified structure that often underlie it.
Abstract: An algorithm for optimizing the Principal Component Analysis in gesture recognition is proposed, which makes use of covariance between factors to reduce data dimensions. The objectivity and automatization of above manual observation is realized by algorithm. We present an approach for the detection and identification of human gestures and describe a working, near gesture recognition system and then recognize the person by comparing characteristics of the gesture to those of known individuals. Our approach treats gesture recognition as a two dimensional recognition problem, taking advantage of the fact that gestures are normally upright and thus may be described by a small set of 2-D characteristics values. With minimal additional effort PCA provides a roadmap for how to reduce a complex data set to a lower dimension to reveal the sometimes hidden, simplified structure that often underlie it. The proposed algorithm is implemented in SystemC language, with the intention to download on to a FPGA. The output of the system developed in SystemC consists of the gesture ID with closest match, as well as value representing how close this match is (Euclidean Distance value). As PCA has been mostly used for face recognition, this technique has been extended to gesture recognition and is quite fast, relatively simple, and has been shown to work well in a somewhat constrained environment.

27 citations

Proceedings ArticleDOI
12 Mar 2015
TL;DR: The output graph of cooling and heating according to time is shown and the approximation of the performance is calculated and this Peltier Module is used in the authors' daily life to save power consumption.
Abstract: Power consumption is one of the major issues in today's general life But semiconductor is a great solution of this power consumption If we success to use semiconductors in well manner then we can reduce power consumption Peltier module is one of the best solutions for this Air-conditioner carry 2000 or 3000 Watt power and cloth iron takes minimum 750 Watt power But due to use of this Peltier module in our system it saves lots of power We can say the cooler gives the temperature of air-conditioner in only approx 200 Watt And cloth iron takes only 50 Watt The performance of these systems is evaluated in the research and also commercialization point of view, reliability of this device and life of this device is discussed in the paper The output graph of cooling and heating according to time is shown in figures 8, 9, and 10 From these graph we can calculate the approximation of the performance and use this Peltier Module in our daily life to save power consumption

17 citations

Proceedings ArticleDOI
01 Jan 2013
TL;DR: In this paper, modeling of DC motor has been done using MATLAB and its speed is controlled by implementing PID (Proportional-Integral-Derivative) controller on FPGA platform.
Abstract: In this paper, modeling of DC motor has been done using MATLAB and its speed is controlled by implementing PID (Proportional-Integral-Derivative) controller on FPGA platform. The hardware used is Spartan-3E (XC3S250E) FPGA board, DC Motor module and ADC. The software tools used are MATLAB, Xilinx ISE 8.1i and Model-Sim SE-EE 5.4a.The PWM signal acts as an input signal for DC Motor. Optical Encoder has been used in feedback path whose output is fed back as an input to the PID Controller. The code has been written in Hardware Descriptive Language, and synthesised by Xilinx ISE 8.1i tool. The results are first simulated and then implemented on FPGA board. Performance analysis of PID Controller step responses has been done using MATLAB.

14 citations

01 Jan 2009
TL;DR: The algorithm for partial reconfiguration flow & implementation of reconfigurable modules (RM) on Xilinx Virtex-4(XC4VFX12) and the implementation results in dramatically increase in speed and functionality of FPGA based system.
Abstract: Reconfigurable computing is an emerging field in this modern world of computer and electronics engineering, which allows the system hardware to be changed periodically in order to execute different applications on the same hardware. Partial reconfiguration is the prerequisite of reconfigurable computing, as it allows time-sharing of physical resources for the execution of multiple design modules. Moreover, partial reconfigurable modules can be swapped in or out on the fly from the operating environment control while other modules in the base design continue functioning without incurring any system downtime. This results in dramatically increase in speed and functionality of FPGA based system. This paper presents the algorithm for partial reconfiguration flow & implementation of reconfigurable modules (RM) on Xilinx Virtex-4(XC4VFX12). All the reconfigurable modules are designed and simulated to verify the functionality with supporting simulation tool on ModelSim-6.0d and synthesized with Xilinx 9.1i (ISE).

14 citations

Journal ArticleDOI
TL;DR: An (2, n, m) multi secret sharing scheme in which exactly n share are generated to encode m secret images in which perfect alignment of shares between shares is not required to obtain secret image.
Abstract: Multi secret sharing is used to hide more than one secret information. In this approach secret information is divided in many parts and distributed among participants. Secret information may be in form of images also. Initially, Visual Cryptography (VC) applied for single secret images. After encryption process of VC, encrypted meaningless images are generated known as shares. Nowadays, multiple secret images may be secured by VC also. However, multi secret sharing schemes provide security to multiple images. Obtaining multiple images by using minimum number of shares is really an existing problem. Existing algorithms are limited to fix number of secret images with minimum number of shares. In this paper, we proposed an (2, n, m) multi secret sharing scheme in which exactly n share are generated to encode m secret images. If set of shares taken from qualified set then secret images revealed on the other hand set of shares taken from forbidden set than no information revealed. Minimum two shares ar...

11 citations


Cited by
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Book
16 Nov 1998

766 citations

Proceedings Article
01 Jan 2003
TL;DR: Three hardware platforms that addresses the needs of wireless sensor netwoks are presented that produces Operating system concepts for refining concurrency mechanisms and the full realization of the general architecture is represented.
Abstract: The Wireless sensor network play a vital role in collecting a Real – Time data, monitoring environmental conditions based on technology adoption. These sensor network is the combination of sensing, computation, and communication through a single tiny device. Here many tiny nodes assemble and configure themselves. It also controls actuators that extend control from cyberspace into the physical world. Here the sensor nodes communicate with the local peers rather than the high – power control tower or base station. Instead, of relying on a predeployed infrastructure, each individual sensor or actuator become part of the overall infrastructure. Here we have three hardware platforms that addresses the needs of wireless sensor netwoks. The operating system here uses an event based execution to support concurrency. The platform serves as a baseline and does not contain any hardware accelerators. . First platform serves as a baseline and it produces Operating system concepts for refining concurrency mechanisms. The second node validates the architectural designs and improve the communicational rates. The third node represents the full realization of the general architecture. Keywords— node, platform, concurrency.

371 citations

Journal ArticleDOI
14 Feb 2020-Sensors
TL;DR: A survey aimed at summarizing the current state of the art regarding smart irrigation systems, which determines the parameters that are monitored in irrigation systems regarding water quantity and quality, soil characteristics and weather conditions.
Abstract: Water management is paramount in countries with water scarcity. This also affects agriculture, as a large amount of water is dedicated to that use. The possible consequences of global warming lead to the consideration of creating water adaptation measures to ensure the availability of water for food production and consumption. Thus, studies aimed at saving water usage in the irrigation process have increased over the years. Typical commercial sensors for agriculture irrigation systems are very expensive, making it impossible for smaller farmers to implement this type of system. However, manufacturers are currently offering low-cost sensors that can be connected to nodes to implement affordable systems for irrigation management and agriculture monitoring. Due to the recent advances in IoT and WSN technologies that can be applied in the development of these systems, we present a survey aimed at summarizing the current state of the art regarding smart irrigation systems. We determine the parameters that are monitored in irrigation systems regarding water quantity and quality, soil characteristics and weather conditions. We provide an overview of the most utilized nodes and wireless technologies. Lastly, we will discuss the challenges and the best practices for the implementation of sensor-based irrigation systems.

264 citations

Journal ArticleDOI

239 citations

Posted Content
TL;DR: In this paper, the authors discuss work done in the area of hand gesture recognition where focus is on the intelligent approaches including soft computing based methods like artificial neural network, fuzzy logic, genetic algorithms etc.
Abstract: Hand gestures recognition (HGR) is one of the main areas of research for the engineers, scientists and bioinformatics. HGR is the natural way of Human Machine interaction and today many researchers in the academia and industry are working on different application to make interactions more easy, natural and convenient without wearing any extra device. HGR can be applied from games control to vision enabled robot control, from virtual reality to smart home systems. In this paper we are discussing work done in the area of hand gesture recognition where focus is on the intelligent approaches including soft computing based methods like artificial neural network, fuzzy logic, genetic algorithms etc. The methods in the preprocessing of image for segmentation and hand image construction also taken into study. Most researchers used fingertips for hand detection in appearance based modeling. Finally the comparison of results given by different researchers is also presented.

141 citations