Bio: Asuha is an academic researcher from Osaka University. The author has contributed to research in topics: Current density & Nitric acid. The author has an hindex of 13, co-authored 16 publications receiving 486 citations.
TL;DR: In this paper, the capacitance and voltage curves for chemical SiO2 layers have been measured due to the low leakage current density, which is due to an increase in the energy discontinuity at the Si/SiO2 interface.
Abstract: Chemical oxidation of Si by use of azeotrope of nitric acid and water can form 1.4-nm-thick silicon dioxide layers with a leakage current density as low as those of thermally grown SiO2 layers. The capacitance–voltage (C–V) curves for these ultrathin chemical SiO2 layers have been measured due to the low leakage current density. The leakage current density is further decreased to ∼1/5 (cf. 0.4 A/cm2 at the forward gate bias of 1 V) by post-metallization annealing at 200 °C in hydrogen. Photoelectron spectroscopy and C–V measurements show that this decrease results from (i) increase in the energy discontinuity at the Si/SiO2 interface, and (ii) elimination of Si/SiO2 interface states and SiO2 gap states.
TL;DR: In this paper, it was shown that poly-SiO2 layers with a uniform thickness can be formed even on a rough surface of polycrystalline Si thin film by direct Si oxidation with nitric acid (HNO3).
TL;DR: In this article, a 3.5-nm-thick SiO2 layer with a higher atomic density of 2.22×1022∕cm2 was formed by immersion of Si in 40 wt% nitric acid (HNO3) followed by immersion in an azeotropic mixture (i.e., 68 wt % HNO3).
Abstract: 3.5-nm-thick SiO2 layers can be formed at 120 °C by immersion of Si in 40 wt % nitric acid (HNO3) followed by immersion in an azeotropic mixture (i.e., 68 wt % HNO3). The former immersion produces a 1.1-nm SiO2 layer with a low atomic density of 2.19×1022∕cm2, where the layer acts as a catalyst for the decomposition of HNO3. The latter immersion results in a 3.5-nm SiO2 layer with a higher atomic density of 2.22×1022∕cm2. When the postmetalization annealing treatment at 250 °C in hydrogen is performed on the ⟨Al∕3.5-nmSiO2∕Si(100)⟩ metal-oxide semiconductor diodes, interface states are passivated and a low leakage current density (e.g., 8×10−4A∕cm2 at the forward gate bias of 1.5 V) is achieved.
TL;DR: In this paper, the leakage current density of the as-grown SiO2 layers of 1.3 nm thickness was investigated and it was concluded that the high atomic density results from the desorption of water and OH species, and oxidation of the suboxide species, both resulting in the formation of SiO 2.
TL;DR: In this paper, the leakage current density of Si-based metal-oxide-semiconductor (MOS) diodes was investigated in the presence of crown-ether cyanide treatment.
Abstract: Crown-ether cyanide treatment, which includes the immersion of Si in KCN solutions containing 18-crown-6 molecules, is found to greatly decrease the leakage current density of Si-based metal–oxide–semiconductor (MOS) diodes. The decrease by one order of magnitude for the single crystalline Si-based MOS diodes is attributable to the elimination of Si/SiO2 interface states by reaction with cyanide ions and formation of Si–CN bonds. The reduction in the leakage current density by two orders of magnitude is caused for polycrystalline Si-based MOS diodes, and this decrease is attributed to the passivation of trap states in poly-Si as well as the interface states.
TL;DR: In this paper, a review of metal-oxide interfaces at temperatures below 1000 ǫC is presented, with special emphasis on model systems like ultrathin metal overlayers or metal nanoclusters supported on well-defined oxide surfaces.
11 Jan 2006
TL;DR: In this article, a memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state, thus leakage is low and assurance is high that no uninitialized memory cells are disturbed.
Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
•31 Dec 2013
TL;DR: In this article, the memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage.
Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.
TL;DR: In this paper, the leakage current of the SiO2 layer formed with 61 wt'% HNO3 at its boiling temperature of 113'°C has a 1.3 nm thickness with a considerably high density leakage current.
Abstract: Ultrathin silicon dioxide (SiO2) layers with excellent electrical characteristics can be formed using the nitric acid oxidation of Si (NAOS) method, i.e., by immersion of Si in nitric acid (HNO3) solutions. The SiO2 layer formed with 61 wt % HNO3 at its boiling temperature of 113 °C has a 1.3 nm thickness with a considerably high density leakage current. When the SiO2 layer is formed in 68 wt % HNO3 (i.e., azeotropic mixture with water), on the other hand, the leakage current density (e.g., 1.5 A/cm2 at the forward gate bias, VG, of 1 V) becomes as low as that of thermally grown SiO2 layers, in spite of the nearly identical SiO2 thickness of 1.4 nm. Due to the relatively low leakage current density of the NAOS oxide layer, capacitance–voltage (C–V) curves can be measured in spite of the ultrathin oxide thickness. However, a hump is present in the C–V curve, indicating the presence of high-density interface states. Fourier transformed infrared absorption measurements show that the atomic density of the SiO...
TL;DR: In this article, the ozone-based oxide layers were applied to the electron-selective contact (n-TOPCon) on planar and textured surfaces, and the oxide properties as stoichiometry and layer thickness were analyzed by means of X-ray photoelectron spectroscopy (XPS), spectral ellipsometry (SE) and transmission electron microscopy (TEM).