Ata Khorami

Bio: Ata Khorami is an academic researcher from Sharif University of Technology. The author has contributed to research in topics: Capacitor & Comparator. The author has an hindex of 11, co-authored 36 publications receiving 294 citations.

High-speed low-power comparator for analog to digital converters

Abstract: A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage , is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator.

A Low-Power High-Speed Comparator for Precise Applications

Abstract: A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

Low-power technique for dynamic comparators

Abstract: A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.

A low-power high-speed comparator for analog to digital converters

Abstract: A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power consumption of the comparator trades with the speed which is simply controlled by the delay of the second stage. As a result, a low-power comparator for given offset and speed requirements can be designed efficiently.

Low-power DAC with charge redistribution sampling method for SAR ADCs

Abstract: A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. This sampling method is proposed to reduce the switching energy. Thanks to the proposed switching method, only one reference voltage (V cm = 1/2V ref) is required which helps to improve the precision of the DAC along with energy reduction compared with those methods that use more than one reference voltage. The switching energy and area of the DAC reduce by 97.66% and 50% compared with the conventional binary weighted DAC.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

High-speed low-power comparator for analog to digital converters

Abstract: A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage , is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator.

A Low-Power High-Speed Comparator for Precise Applications

Abstract: A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

Abstract: Low-power, high-speed dynamic comparators are highly desirable in the design of high-speed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides strong positive feedback, to accelerate the comparison and reduce the static power consumption. The delay of the comparator is mainly determined by the total effective transconductance of the latching stage. The delay not only limits the maximum operating frequency but also extends the period of the metastable state of the latching stage; hence, it increases energy consumption. However, at the beginning of the comparison phase, the conventional latching stage has two transistors with zero gate-to-source voltage, which degrade the total effective transconductance of the latching stage. In this paper, a novel low-power, high-speed dynamic comparator with a new latching stage is presented. The proposed latching stage uses separated gate-biasing cross-coupled transistors instead of the conventional cross-coupled inverter structure. The simple proposed latching stage improves its effective total transconductance at the beginning of the comparison phase, which leads to a much faster comparison and lowers energy consumption. The comparator is analyzed and compared to its prior type in terms of delay and power consumption via simulations and measurements. The experimental results demonstrate that the proposed comparator operates from a 1.2-V supply and consumes 110-fJ energy per comparison, with sampling speeds up to 2 GS/s.

Low-power technique for dynamic comparators

Abstract: A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.