Atanu Majumder

Bio: Atanu Majumder is an academic researcher from Information Technology University. The author has contributed to research in topics: Hardware Trojan & Cloud computing. The author has an hindex of 3, co-authored 8 publications receiving 24 citations. Previous affiliations of Atanu Majumder include University of Calcutta.

Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan Attacks

Abstract: The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) has made it feasible to execute various mixed critical tasks on the same platform. This requires partitioning the FPGA fabric into several virtual portions (VPs) and a scheduling methodology to determine which task is to be executed when and in which FPGA VP. Executing a task in an FPGA VP requires runtime configuring of the VP with a bitstream or a reconfigurable intellectual property, procured from a third party intellectual property (3PIP) vendor. Recent literature has exposed the presence of malicious elements like hardware trojan horses (HTHs) in such 3PIP bitstreams. Such HTH is particularly dangerous as these remain dormant during testing and initial stages of operation, but gets activated suddenly at runtime to jeopardize the basic security primitives of the system. Thus, reliability driven mixed critical tasks processing on FPGAs against HTH attacks is important. Firstly, reliability driven mixed critical periodic task schedule generation against HTH attacks is focused. Secondly, reliability ensured execution of mixed critical aperiodic and sporadic tasks in the generated periodic task schedule is considered. Experimentation is carried out with a variety of bitstreams and performance evaluation is performed via metrics like task success rate, task rejection rate and task preemption rate.

Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks

Abstract: The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.

EAAM: Energy-aware application management strategy for FPGA-based IoT-Cloud environments

Abstract: An efficient integration of Internet of Things (IoT) and cloud computing techniques accelerates the evolution of next-generation smart environments (e.g., smart homes, buildings, cities). The advanced modern cloud networking architecture also helps to efficiently host, manage and optimize the IoT services in smart environments. In this paper, we have considered an “IoT-Cloud” environment where servers are composed of Field Programmable Gate Arrays (FPGAs) which are reconfigurable in nature. The energy consumption is considered as a major driving factor for the operational cost of the “IoT-Cloud” platform. We have proposed an “energy-aware application management” strategy for FPGA-based IoT-Cloud environments, which can efficiently handle sensors’ data transmission by positioning them into the best possible coordinates and execute the Service Requests requested by the users. We have compared our strategy performances with an existing technique and the results show that our proposed strategy is capable to achieve high resource utilization with low energy consumption over different simulation scenarios.

Auction Based Power Aware Real-Time Scheduler for Heterogeneous FPGA Cloud Platform

Abstract: Auction based scheduling strategies in current literature are essentially associated with software for cloud environments, as the underlying hardware is considered generic and not re-configurable at runtime. However, recent cloud infrastructures like Amazon EC2 F1 services and Microsoft Azure deploy field programmable gate arrays (FPGAs) as an integral component, for its property of dynamic re-configuration at runtime. Auction based scheduling strategies for FPGA based cloud platforms is still not explored, where the goal is to optimize power dissipation. In this work, we try to deploy an auction based power aware scheduling mechanism for real-time task scheduling in heterogeneous FPGA based cloud platforms, which we term "Auction Based Power Aware Real-Time Scheduler" (AB-PARTS). In this mechanism, a local scheduler is invoked to execute requested tasks (periodic and non-periodic) to meet its real-time requirements. If tasks cannot be guaranteed execution in the local processing elements (PEs) or FPGAs, switch to a distributed scheduling approach with an auction scheme is made. In the auction scheme, task details are broadcasted to other schedulers, which send back an acknowledgment with reward value based on the dynamic status of the PEs of the schedulers. Task is dispatched to the scheduler, which generates the maximum reward value. The scheduler allocates the task to its PEs in such a manner so that the power consumption is optimized. For experimental purpose, we deploy a cloud platform with heterogeneous Altera FPGA boards, where performance of the proposed strategy is tested with standard tasks of the EPFL benchmark suite. Related results depict that the strategy is quite capable to achieve high resource utilization with low power consumption over different simulation scenarios.

Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications

Abstract: The internet of things (IoTs)-based systems require battery-enabled energy-efficient memory circuits to operate at low voltage domain, especially below the transistor’s threshold. This study presents a single-ended 7T SRAM cell for IoTs applications. Cell core of the proposed 7T SRAM cell is composed of a novel Schmitt-trigger circuit in which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. The proposed 7T SRAM cell employs only one bitline to perform both read and write operations to reduce active power consumption. Read operation of the proposed 7T SRAM cell is conducted using only a single n-type MOSFET transistor driven by QB node. This transistor isolates bitline from storage nodes during read operation, improving read stability (RSNM) and read delay (TRA). A p-type MOSFET controlled by write wordline is placed inside the cell core to cut its feedback path off during write operation. This mechanism eliminate writing ‘1′ issue in single-ended SRAM cell and facilitate write ‘1′ operation, resulting in write-ability (WSNM) enhancement. To prove superiority of the proposed 7T SRAM cell in the various design metrics, it is compared with six state-of-the-art SRAM cells at subthreshold supply of VDD = 0.3 V. The proposed 7T SRAM cell is the second/first/third best cell in terms of RSNM/WSNM/write access time (TWA). Furthermore, an improvement of at least 2.55X in TRA and 12.58X (2.02X) in read (write) energy consumption is achieved by the proposed 7T SRAM cell. Although, the proposed 7T SRAM cell offers some disadvantages, nevertheless it offers the best proposed figure of merit.

Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper

Abstract: With the advancement of technology scaling, multi/many-core platforms are getting more attention in embedded systems due to the ever-increasing performance requirements and power efficiency. This feature size scaling, along with architectural innovations, has dramatically exacerbated the rate of manufacturing defects and physical fault-rates. As a result, in addition to providing high parallelism, such hardware platforms have introduced increasing unreliability into the system. Such systems need to be well designed to ensure long-term and application-specific reliability, especially in mixed-criticality systems, where incorrect execution of applications may cause catastrophic consequences. However, the optimal allocation of applications/tasks on multi/many-core platforms is an increasingly complex problem. Therefore, reliability-aware resource management is crucial while ensuring the application-specific Quality-of-Service (QoS) requirements and optimizing other system-level performance goals. This article presents a survey of recent works that focus on reliability-aware resource management in multi-/many-core systems. We first present an overview of reliability in electronic systems, associated fault models and the various system models used in related research. Then, we present recent published articles primarily focusing on aspects such as application-specific reliability optimization, mixed-criticality awareness, and hardware resource heterogeneity. To underscore the techniques’ differences, we classify them based on the design space exploration. In the end, we briefly discuss the upcoming trends and open challenges within the domain of reliability-aware resource management for future research.

Modular dynamic reconfiguration in Virtex FPGAs

Abstract: Modular systems implemented on field-programmable gate arrays (FPGAs) can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. Although dynamic partial reconfiguration is possible in Virtex and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. Two methods for implementing modular reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, developed recently, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of dynamic reconfiguration. The cost of this advancement is increased reconfiguration time. The second method has been demonstrated in three applications, including the first reported implementation of modular reconfiguration in a Virtex-4 device.

Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks

Abstract: The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.