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Principles Of Optics Electromagnetic Theory Of Propagation Interference And Diffraction Of Light

Preface 1. Wave Theory of Optical Waveguides 2. Planar Optical Waveguides 3. Optical Fibers 4. Couple Mode Theory 5. Nonlinear Optical Effects in Optical Fibers 6. Finite Element Method 7. Beam Propagation Method 8. Staircase Concatention Method 9. Planar Lightwave Circuits 10. Theorems and Formulas Appendix

Fundamentals of optical waveguides

Solid State Communications 112 (1999) 383–386

Si Nano-Photodiode with a Surface Plasmon Antenna

Wireless device technology operating in the millimetre-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Here we report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Our devices also offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power. Radio-frequency transistors made from aligned carbon nanotubes offer high linearity and an extrinsic cutoff frequency of over 100 GHz.

Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz

A comprehensive review of the main existing devices, based on the classic and new related Hall Effects is hereby presented. The review is divided into sub-categories presenting existing macro-, micro-, nanoscales, and quantum-based components and circuitry applications. Since Hall Effect-based devices use current and magnetic field as an input and voltage as output. researchers and engineers looked for decades to take advantage and integrate these devices into tiny circuitry, aiming to enable new functions such as high-speed switches, in particular at the nanoscale technology. This review paper presents not only an historical overview of past endeavors, but also the remaining challenges to overcome. As part of these trials, one can mention complex design, fabrication, and characterization of smart nanoscale devices such as sensors and amplifiers, towards the next generations of circuitry and modules in nanotechnology. When compared to previous domain-limited text books, specialized technical manuals and focused scientific reviews, all published several decades ago, this up-to-date review paper presents important advantages and novelties: Large coverage of all domains and applications, clear orientation to the nanoscale dimensions, extended bibliography of almost one hundred fifty recent references, review of selected analytical models, summary tables and phenomena schematics. Moreover, the review includes a lateral examination of the integrated Hall Effect per sub-classification of subjects. Among others, the following sub-reviews are presented: Main existing macro/micro/nanoscale devices, materials and elements used for the fabrication, analytical models, numerical complementary models and tools used for simulations, and technological challenges to overcome in order to implement the effect in nanotechnology. Such an up-to-date review may serve the scientific community as a basis for novel research oriented to new nanoscale devices, modules, and Process Development Kit (PDK) markets.

https://www.mdpi.com/1424-8220/20/15/4163/pdf

A Comprehensive Review of Integrated Hall Effects in Macro-, Micro-, Nanoscales, and Quantum Devices.

Silicon-on-insulator (SOI) and bulk metal–oxide–semiconductor (MOS) transistors were fabricated simultaneously and tested electrically and optically at room temperature. The electroluminescence (EL) spectrum has been measured in both types of devices. A visible emitted radiation was observed when both devices were operated in the avalanche breakdown mode. In the case of SOI device, five different peaks at a photon energy of 2.31, 2.06, 1.81, 1.63, and 1.50 eV were observed. The regular spacing between the measured peaks indicates cavity effects due to the various layers of the SOI MOS transistor structure. The thin silicon layer thickness of 400 A seems to be responsible for the factor of about 16 in the EL intensity of the SOI device as compared to the bulk device.

Enhanced electroluminescence in silicon-on-insulator metal–oxide–semiconductor transistors with thin silicon layer

The simulation of silicon-based light-emitting and photodetectors nanodevices using computer algebra became a challenge. These devices couple the hyperbolic equations of electromagnetic radiation, the parabolic equations of heat conduction, the elliptic equations describing electric potential, and the eigenvalue equations of quantum mechanics—with the nonlinear drift–diffusion equations of the semiconductor physics. These complex equations must be solved by using generally mixed Dirichlet–Neumann boundary conditions in three-dimensional geometries. Comsol Multiphysics modeling software is employed integrated with MATLAB–SIMULINK and Zemax. The physical equations are discretized on a mesh using the Galerkin finite element method (FEM) and to a lesser extent the method of finite volumes. The equations can be implemented in a variety of forms such as directly as a partial differential equation, or as a variational integral, the so-called weak form. Boundary conditions may also be imposed directly or using variational constraint and reaction forces. Both choices have implication for convergence and physicality of the solution. The mesh is assembled from triangular or quadrilateral elements in two-dimensions, and hexahedral or prismatic elements in three dimensions, using a variety of algorithms. Solution is achieved using direct or iterative linear solvers and nonlinear solvers. The former are based on conjugate gradients, the latter generally on Newton–Raphson iterations. The general framework of FEM discretization, meshing and solver algorithms will be presented together with techniques for dealing with challenges such as multiple time scales, shocks and nonconvergence; these include load ramping, segregated iterations, and adaptive meshing.

Computer Algebra Challenges in Nanotechnology: Accurate Modeling of Nanoscale Electro-optic Devices Using Finite Elements Method

We compare two extraction methods based on the Y-function technique to extract the massive (>100 kΩ) series resistance observed in SOI-MOSFET devices. A part the application of these methods for such high series resistance, the novelty in this paper is that our methods are based on the I DS  −  V GS characteristics measured for several drain voltages in the linear domain, while the classic methods are based on characteristics measured for several channel length. Here, we compare two types of SOI-MOSFET devices: Ultra-Thin Body (UTB) and Nano-Scale Body (NSB) sharing same W / L ratio but having a channel thickness of 46 nm and 1.6 nm, respectively. These devices were fabricated simultaneously on the same silicon wafer using a selective “gate recessed” process. Their respective current–voltage characteristics measured at room temperature were found to be different by several orders of magnitude. In this paper, we show that, by using two kinds of Y-function based methods, the I DS  −  V GS characteristics of NSB can be analytically modeled by a massive series resistance depending on the gate voltage.

Application, modeling and limitations of Y-function based methods for massive series resistance in nanoscale SOI MOSFETs

The constantly growing use of real-time computing generates constant urge for much faster processors than those which are currently available in the market. Correspondingly, there is an accelerated development of new optics communication related applications and components. The effort to combine those two trends leads to the generation of new optoelectronic nanodevices. Such hybrid devices may allow high operation speed, reduced cross talk and other noises, low operation power, and obviate the need for the existing electro-optical convertors. In this letter, we present the design, simulation, fabrication, and characterization of an optoelectronic device based on silicon which is capable of speeding up the processing capabilities. This novel device is called silicon-on-insulator photo-activated modulator. The nature of the data flow in this device is electronic, while the modulation control command is optic. Since the external voltage in the final configuration design of the device is constant and no $RC$ (electrical average response time) related delay is generated, faster operation rates are anticipated. This novel device can serve as a building block toward the development of optical data processing while breaking through the way to all optic processors based on silicon chips that are fabricated via typical microelectronics fabrication process.

Avi Karsenty

Papers

A Comprehensive Review of Integrated Hall Effects in Macro-, Micro-, Nanoscales, and Quantum Devices.

Enhanced electroluminescence in silicon-on-insulator metal–oxide–semiconductor transistors with thin silicon layer

Computer Algebra Challenges in Nanotechnology: Accurate Modeling of Nanoscale Electro-optic Devices Using Finite Elements Method

Application, modeling and limitations of Y-function based methods for massive series resistance in nanoscale SOI MOSFETs

Nanoscale Silicon-on-Insulator Photo-Activated Modulator Building Block for Optical Communication