Showing papers by "Avram Bar-Cohen published in 2009"

Modeling and Prediction of Two-Phase Microgap Channel Heat Transfer Characteristics

Abstract: A detailed analysis of microchannel/microgap heat transfer data for two-phase flow of refrigerants and dielectric liquids, gathered from the open literature and sorted by the Taitel and Dukler flow regime mapping methodology, is performed. Annular flow is found to be the dominant regime for this thermal transport configuration and to grow in importance with decreasing channel diameter. A characteristic M-shaped heat transfer coefficient variation with quality (or superficial velocity) for the flow of refrigerants and dielectric liquids in miniature channels is identified. The inflection points in this M-shaped curve are seen to equate approximately with flow regime transitions, including a first maximum at the transition from Bubble to Intermittent flow and a second maximum at moderate qualities in Annular flow, just before local dryout begins. The predictive accuracy of five classical two-phase heat transfer correlations for miniature channel flow is examined. Selecting the best fitting of the classical ...

On-chip Hot Spot Remediation with Miniaturized Thermoelectric Coolers

Abstract: The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in chip heat flux and growing concern over the emergence of on-chip “hot spots” in microprocessors, along with such high flux regions in power electronic chips and LED’s. Miniaturized thermoelectric coolers (μ-TEC’s) are a most promising cooling technique for the remediation of such hot spots. This paper presents a comprehensive review of recent advances in novel applications of superlattice, mini-contact, and silicon-based miniaturized thermoelectric coolers in reducing the severity of on-chip hot spots.

Mini-Contact Enhanced Thermoelectric Coolers for On-Chip Hot Spot Cooling

Abstract: Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors, have led to on-chip high heat flux “hot spots,” which have emerged as the primary driver for thermal management of today's integrated circuit (IC) technology. This article describes the use of a mini-contact to enhance the cooling flux of a miniaturized thermoelectric cooler (TEC) for on-chip hot-spot remediation. A package-level numerical simulation is developed to predict the on-chip hot spot cooling capability achievable with such a mini-contact enhanced TEC. Attention is focused on the hot-spot temperature reduction associated with variations in mini-contact size and thermoelectric element height, as well as the parasitic effect from the thermal contact resistance introduced by the mini-contact. A preliminary experiment has been conducted to verify the numeric model and to demonstrate the effects of the mini-contact on hot-spot cooling.

Effects of Temperature Cycling and Elevated Temperature/Humidity on the Thermal Performance of Thermal Interface Materials

Abstract: Thermal interface materials (TIMs) have become increasingly important in reducing the interfacial thermal resistance between contacting surfaces inside electronic devices, such as at the die-heat-sink or heat-spreader-heat-sink interfaces. While the focus regarding implementing TIMs remains on reducing the thermal resistance path, the long-term performance of the TIM is important from a life-cycle standpoint. This paper presents test and analysis results examining the effect of temperature cycling and elevated temperature/humidity on the thermal performance of filled polymer TIMs using the laser flash method. A three-layer sandwich structure was used to simulate loading conditions encountered by TIMs in actual applications and to assess the change in their thermal resistances. The evaluated thermal resistance included contact and bulk resistances and was calculated using the Lee algorithm, an iterative method that uses the properties of the single layers and the three-layer sandwich structures. Test samples included three thermal putties, a gap filler, an adhesive, a gel, and two gap pads. For most materials, little change or slight improvement in the thermal performance was observed over the course of environmental exposures. Scanning acoustic microscope images revealed delamination in one group of gap pad samples and cracking in the putty samples as a result of temperature cycling. One thermal putty material showed degradation due to temperature cycling resulting from bulk material changes near the glass transition temperature, while other samples showed little change or slight improvement in the thermal performance over the course of temperature cycling.

Thermal Management of On-Chip Hot Spot

Abstract: The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip “hot spots”. The application of on-chip high heat flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric microcoolers — using mini-contcat enhancement and in-plane thermoelectric currents, orthotropic TIM’s/heat spreaders, and phase-change microgap coolers.Copyright © 2009 by ASME

Thermal management of on-chip hot spots and 3D chip stacks

Abstract: The rapid increase in on-chip heat fluxes and package heat density, accompanying the migration to nanoelectronics and 3D chip stacks, has placed thermal management squarely on the critical path for advanced product development. Innovative, cost-effective cooling techniques, combined in a synergetic way with more conventional approaches, must be developed if the benefits of the Moore's Law progression are to be realized. Following a brief discussion of the industry roadmap for IC packaging and review of chip package thermal management options, attention will turn to the application of solidstate thermoelectric refrigeration and the thermal characteristics of direct immersion cooling in dielectric liquids. The presentation will close with a discussion of the research challenges associated with the commercial implementation of on-chip thermoelectric coolers and direct liquid cooling.

Passive Immersion Cooling of 3-D Stacked Dies

Abstract: Three-dimensional die stacking increases integrated circuit (IC) density, providing increased capabilities and improved electrical performance on a smaller printed circuit board (PCB) footprint area. However, these advantages come at the expense of higher volumetric heat generation rates and decreased thermal and mechanical access to the die areas. Passive immersion cooling, allowing for buoyancy-driven fluid flow between stacked dies, can provide high heat transfer coefficients directly on the die surfaces, can easily accommodate a wide variety of interconnect schemes, and is scalable to any number of dies. A methodology for the optimization of immersion cooled 3-D stacked dies is presented, including the effects of confinement on natural convection and channel boiling. Optimum die spacings for both single and two phase cooling with saturated FC-72 are found to be on the order of half a millimeter for typical microelectronics geometries and to yield heat densities of 10-50 W/cm3 in natural convection and 100-500 W/cm3 in channel boiling.

Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

Abstract: Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2 . The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.Copyright © 2009 by ASME

Direct liquid thermal management of 3D chip stacks

Abstract: Chip stacks are a crucial building block in advanced 3D microsystem architectures and can accommodate shorter interconnect distances between devices, reduced power dissipation, and improved electrical performance. Although enhanced conduction can serve to transfer the dissipated heat to the top and sides of the package and/or down to the underlying PCB, effective thermal management of stacked chips remains a most difficult challenge. Immersion cooling techniques, which provide convective and/or ebullient heat transfer, along with buoyant fluid flow, in the narrow gaps separating adjacent chips, are a most promising alternative to conduction cooling of three-dimensional chip stacks. Application of the available theories, correlations, and experimental data are shown to reveal that passive immersion cooling-relying on natural convection and/or pool boiling — could provide the requisite thermal management capability for 3D chip stacks anticipated for use in much of the portable equipment category. Alternatively, pumped flow of dielectric liquids through the microgaps in 3D stacks, providing single phase and/or flow boiling heat absorption, could meet many of the most extreme thermal management requirements for highperformance 3D microsystems. Use of deionized water is shown to provide an order of magnitude improvement in heat dissipation relative to the available dielectric fluids.

Thermal Imaging of Two-Phase Coooled Microgap Channel Wall

Abstract: The forced flow of dielectric liquids, undergoing phase change while flowing in a narrow channel formed between chips or a chip and a passive cover, is a promising candidate for the thermal management of high heat flux semiconductor devices. These microgap configurations provide direct contact — and hence highly efficient cooling — between a chemically-inert, dielectric liquid and the back surface of an active electronic component. However, the two-phase flow phenomena that establish the upper bound on the cooling capability of such microgap coolers are only poorly understood. In the present study, IR images of the heated surface of a two-phase microgap channel, 260 μm × 30 mm × 34mm, are obtained, through a sapphire window on the opposing wall of the channel Corrections are made for the reflection and absorption of IR radiation by the two-phase mixture flowing in the channel. Previously undetected spatial and temporal temperature variations, approaching 20 K, were observed on the surface of the microgap channel for heat fluxes of 3.2 W/cm2 and FC-72 mass flux of 35 kg/m2 s. The frequency and amplitude of the observed temperature variations appear to reflect the complexity of the prevailing thermal transport phenomena and may provide evidence of local dryout in high quality annular flow in miniature channels.Copyright © 2009 by ASME

Minimum Energy Design for Manufacturability of Air Cooled Heat Sinks

Abstract: The substantial material stream, and energy consumption, associated with the cooling of desktop computers, servers, routers, and power electronic modules contribute significantly to the depletion of key resources. To reduce this severe environmental impact, while meeting the thermal management requirements of these components and systems, it is essential that a minimum energy, design-for-manufacturability approach be followed in the design and commercialization of such air-cooled heat sinks. In this paper, a design-for-manufacturability methodology (DFM) is combined with a least-energy optimization methodology, using the total Coefficient of Performance (COPT ), to identify practical low energy designs and existing gaps in manufacturing capability that prevent the attainment of the ideal minimum energy solutions. The COPT methodology relates the heat sink cooling capability to the invested fan pumping work and the thermodynamic work required to manufacture and assemble the heat sink and seeks to maximize the thermal energy that can be extracted from a specified space, while minimizing the material and energy consumed in the fabrication and operation of the specified heat sink. This combined methodology was applied to aluminum, copper, and magnesium as potential heat sink materials for a fixed input work of 20 kWh, and for three different duty cycles, namely, sporadic (1500 h), periodic (6000 h), and continuous (26208 h), respectively. The results presented herein, are derived for heat sinks on a 10 cm by 10 cm isothermal base, and 5 cm fin height, operating at an excess temperature of 25 K relative to the inlet air. The thermo-fluid analysis of the forced convection rectangular plate-fin array has been carried out using a well-validated semi-analytical model. The energy-optimal aluminum, copper and magnesium designs are compared to draw quantitative and qualitative conclusions.Copyright © 2009 by ASME