Avram Bar-Cohen

TL;DR: In this paper, the fatigue life of an underfilled flip-chip package has been evaluated using the Coffin-Manson relation and finite element modeling (FEM)-computed solder shear strain for typical flip chip structures.

TL;DR: Particle layering is introduced as an effective and convenient technique for enhancing boiling nucleation on a surface as discussed by the authors, which can be applied without stress or damage to a surface, it can be implemented in immersion cooling, with boiling, of electronic equipment components.

TL;DR: The Thermal Challenges in Next Generation Electronic Systems (THERMES) workshop as discussed by the authors focused on thermal management roadmaps, micro-scale cooling systems, numerical modeling from the component to system levels, hardware for future high performance and Internet computing architectures, and transport issues in the manufacturing of electronic packages.

TL;DR: In this paper, the authors compared single-phase and two-phase cold plates for a specified inverter module, consisting of 12 pairs of silicon insulated gate bipolar transistor (IGBT) devices and diodes.

TL;DR: In this article, a three-dimensional analytical thermal model of the silicon chip was developed and used to predict the on-chip hot spot cooling performance, and the effects of hot spot size, hot spot heat flux, silicon chip thickness, microcooler size, doping concentration in the silicon, and parasitic Joule heating from electric contact resistance on the cooling of onchip hot spots, were investigated in detail.