This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

A process for producing a semiconductor article is provided which comprises the steps of bonding a film onto a substrate having a porous semiconductor layer, and separating the film from the substrate at the porous semiconductor layer by applying a force to the film in a peeling direction.

Process for producing semiconductor article

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

Basic mechanisms involved in the Smart-Cut® process

Silicon On Insulator technologies appear to be a key issue for low-power, low-voltage technologies (/spl ap/1.5 V) and will play a major role in ULSI developments. Today two SOI material technologies are in competition in the very thin SOI film market: SIMOX (Separation by IMplanted OXygen) and BESOI (Bond and Etch Back SOI) Technology. We have developed a new SOI material technology using a bonding technique combined with an ion implantation step, which aims to overcome the remaining limitations of both the above techniques. This process was developed as the "IMPROVE" (IMplanted PROtons Voids Engineering) process and is henceforth referred to as "Smart-cut". The process is implemented for fabrication of Unibond wafers.

"Smart cut": a promising new SOI material technology

Proton implantation and thermal annealing of silicon result in the formation of a specific type of extended defects involving hydrogen, named “platelets” or “cavities.” These defects have been related to the exfoliation mechanism on which a newly developed process to transfer thin films of silicon onto various substrates is based. The density and the size of these platelets depend on the implantation and annealing conditions. In this letter, rigorous statistical methods based on transmission electron microscopy have been used to quantitatively study the thermal behavior of these defects. Upon annealing, it is shown that the cavities grow in size, reduce their density, while the overall volume they occupy remains constant. This phenomenon is due to a conservative ripening of the cavities. The transfer of hydrogen atoms from small to large cavities leads to a decrease of the elastic energy within the implanted layer while the strain locally increases around the projected range of the protons.

A transmission electron microscopy quantitative study of the growth kinetics of H platelets in Si

The feasibility of transferring patterned and multilayered thin films, simulating part of the stacked structure of a CMOS integrated circuit, from their original bulk silicon substrate to a final substrate, was demonstrated using the Smart-Cut process.

Transfer of structured and patterned thin silicon films using the smart-cut process

For the first time, transfer of a thin monocrystalline GaAs film from its original bulk substrate onto a silicon substrate was achieved by proton implantation and wafer bonding. Successful transfers of 3 in GaAs film are presented.

B. Aspar

Papers

Basic mechanisms involved in the Smart-Cut® process

"Smart cut": a promising new SOI material technology

A transmission electron microscopy quantitative study of the growth kinetics of H platelets in Si

Transfer of structured and patterned thin silicon films using the smart-cut process

Transfer of 3 in GaAs film on silicon substrate by proton implantation process