B. Barnes

Bio: B. Barnes is an academic researcher from Fermilab. The author has contributed to research in topics: Vector control & Data acquisition. The author has an hindex of 2, co-authored 3 publications receiving 12 citations.

Multichannel vector field control module for LLRF control of superconducting cavities

Abstract: The field control of multiple superconducting RF cavities with a single Klystron, such as the proposed RF scheme for the ILC, requires high density (number of RF channels) signal processing hardware so that vector control may be implemented with minimum group delay. The MFC (Multichannel Field Control) module is a 33- channel, FPGA based down-conversion and signal processing board in a single VXI slot, with 4 channels of high speed DAC outputs. A 32-bit, 400MHz floating point DSP provides additional computational and control capability for calibration and implementation of more complex control algorithms. Multiple high speed serial transceivers on the front panel and the backplane bus allow a flexible architecture for inter-module real time data exchanges. An interface CPLD supports the VXI bus protocol for communication to a SlotO CPU, with Ethernet connections for remote in system programming of the FPGA and DSP as well as data acquisition.

A Vector Control and Data Acquisition System for the Multicavity LLRF System for Cryomodule1 at Fermilab

Abstract: A LLRF control and data acquisition system for the 8cavity cryomodule1 at the ILCTA has been implemented using three 33-channel ADC boards in a VXI mainframe. One card each is dedicated to the cavity probes for vector control , forward power and reverse power measurements. The system is scalable to 24 cavities or more with the commissioning of cryomodules 2 and 3 without additional hardware. The signal processing and vector control of the cavities is implemented in an FPGA and a high speed data acquisition system with up to 100 channels which stores data in external SDRAM memory. The system supports both pulsed and CW modes with a pulse rate of 5Hz. Acquired data is transferred between pulses to auxiliary systems such as the piezo controller through the VXI slot0 controller. The performance of the vector control system is evaluated and the design of the system is described.

Design and Evaluation of the Low-Level RF Electronics for the ILC Main LINAC

Abstract: The proposed 30 km long ILC electron/positron collider is pushing the limits not only in basic physics research but also in engineering. For the two main LINACs, the pulsed RF power that is feeding the high number of SC RF cavities (~ 17 000) must be regulated to app. 0.1% for amplitude and 0.2o for phase. This guarantees the required energy spread (0.1%) at the interaction point in the detector. The regulation of phase and amplitude is carried out by the analog/digital electronics also denoted as the low-level RF control system. Besides meeting the regulation specifications, the low-level RF must be reliable, robust and low cost. In the paper we present a possible hardware solution that addresses these issues. The system is evaluated on a cavity emulator implemented on the FPGA. We also present measurement carried out at AØ photo injector.

High-speed data processing module for LLRF

Abstract: Linear accelerators, like the Free-electron LASer in Hamburg (FLASH) or the European X-Ray Free Electron Laser (E-XFEL) take advantage of the digital Low Level Radio Frequency (LLRF) system to control the phase and amplitude of an electromagnetic field inside superconducting cavities. The real-time control LLRF system, processing data within a few microseconds, has to fulfil performance requirements and provide comprehensive monitoring and diagnostics. The AMC-based controller (DAMC-TCK7) board was developed as a general purpose high-performance low-latency data processing unit designed according to the PICMG MTCA.4 spec. The module provides the processing power, data memory, communication links, reference clock, trigger and interlock signals that are required in modern LLRF control systems. The module was originally designed as a cavity field stabilizing controller for standing-wave linear accelerators. However, the application of the board is much wider because it is a general purpose data processing module suitable for systems requiring low latency and high-speed digital signal processing. According to authors’ knowledge this is the first MTCA.4 module offering 12.5 Gbps links, unified Zone 3 connectivity and advanced Module Management Controller proposed by DESY. The DAMC-TCK7 card was used as a hardware template for the development of the other AMC modules of the XFEL accelerator’s LLRF system. This paper discusses the requirements for the digital real-time data processing module, presents the laboratory performance evaluation and verification in Cryo-Module Test Bench (CMTB) at DESY.

A 96 channel receiver for the ILCTA LLRF system at fermilab

Abstract: The present configuration of an ILC main LINAC RF station has 26 nine cell cavities driven from one klystron. With the addition of waveguide power coupler monitors, 96 RF signals will be down-converted and processed. A down-converter chassis is being developed that contains 12 eight-channel analog modules and a single up- converter module. This chassis will first be deployed for testing a cryomodule composed of eight cavities located at New Muon Laboratory (NML) - Fermilab. Critical parts of the design for LLRF applications are identified and a detailed description of the circuit with various characteristic measurements is presented. The board is composed of an input band-pass filter centered at 1.3 GHz, followed by a mixer, which down-converts the cavity probe signal to a proposed 13 MHz intermediate frequency. Cables with 8 channels per connector and good isolation between channels are being used to interconnect each down-converter module with a digital board. As mixers, amplifiers and power splitters are the most sensitive parts for noise, nonlinearities and crosstalk issues, special attention is given to these parts in the design of the LO port multiplication and distribution.

Design and evaluation of a low-level RF control system analog/digital receiver for the ILC main Linacs

Abstract: The proposed RF distribution scheme for the two 15 km long ILC LINACs uses one klystron to feed 26 superconducting RF cavities operating at 1.3 GHz. For a precise control of the vector sum of the signals coming from the SC cavities, the control system needs a high-performance, low-cost, reliable and modular multichannel receiver. At Fermilab we developed a 96-channel, 1.3 GHz analog/digital receiver for the ILC LINAC LLRF control system. In this paper we present a balanced design approach to the specifications of each receiver section, the design choices made to fulfill the goals and a description of the prototyped system. The design is tested by measuring standard performance parameters, such as noise figure, linearity and temperature sensitivity. Measurements show that the design meets the specifications and it is comparable to other similar systems developed at other laboratories, in terms of performance.

LLRF Design for the HINS-SRF Test Facility at Fermilab

Abstract: The High Intensity Neutrino Source (HINS) R&D program requires super conducting single spoke resonators operating at 325 MHz (SSR1) [1]. After coupler installation, these cavities are tested at the HINS-SRF facility at Fermilab. The LLRF requirements for these tests include support for continuous wave and pulsed mode operations, with the ability to track the resonance frequency of the tested cavity. Real-time measurement of the cavity loaded Q and Q0 are implemented using gradient decay techniques, allowing for Q0 versus Eacc plots. A real time cavity simulator was also developed to test the LLRF system and verify its functionality. LLRF SYSTEM OVERVIEW The LLRF system is depicted in Fig. 1. The 325 MHz RF reference is provided by a signal generator (Aeroflex IFR 2023A), for tunability. The master oscillator and local oscillator chassis distributes the 325 MHz reference signal and generates the 338 MHz LO. The LO is obtained by mixing the 325 MHz RF signal with a 13 MHz intermediate frequency (IF), internally generated by dividing the 325 MHz reference by 25. This allows the LO to track the RF signal when it is tuned to match the cavity resonance frequency.

Survey of LLRF development for the ILC

Abstract: The key to a successful LLRF design for the International Linear Collider (ILC) relies on a combined effort from the different laboratories involved in this global project. This paper covers the ILC LLRF design progress both long term and for current test facilities around the world. The SIMCON controller board, originally developed at DESY has been successfully used at FNAL to control superconducting capture cavity I and II. LLRF team leaders from DESY, KEK and FNAL have worked together toward a common design and costing estimate for the ILC LLRF. This paper gives a general overview of the LLRF development achieved through continuous collaboration and communication between the various labs involved in the ILC LLRF design process.