B. Gentinne

Bio: B. Gentinne is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 6, co-authored 15 publications receiving 285 citations.

Design of SOI CMOS operational amplifiers for applications up to 300/spl deg/C

Abstract: Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300/spl deg/C The dependence of these parameters on temperature is first described A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300/spl deg/C for applications such as micropower (below 4 /spl mu/W at 12 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

Abstract: This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

SOI technology for high-temperature applications

Abstract: This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300°C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers

Design and application of SOI CMOS OTAs for high–temperature environments

Abstract: Special techniques are presented for the design of SOI CMOS OTAs which have to operate from room up to very high ambient temperatures. The results of several implementations are reported including applications such as in bandgap and current references as well as Σ-Δ modulators with efficient switch design at elevated temperatures.

Performances of Fully-Depleted Soi Analog Operational Amplifiers

Abstract: b,l=55 nm, b,2=400 nm, and Na=8x1016 and 4x1016 cm-3 for the n- and p-channel devices, respectively. Table 1 presents different measured parameters of the input transistors (Ibis, gm), output transistors (Gut) and the op-amp (gain and fT). It can be seen that the twin-gate configuration improves the output impedance by a factor of two at least, and that it also improves the transconductance at the highest current biases. The impact of this can clearly be seen on the op-amp performances, since the twin-gate devices shows a higher gain than regular FD SO1 devices (up to 10 dB). This is mostly due to the reduction of the output conductance at high drain bias in the twin-gate configuration (the operating point is at VDSS~V) (Figure 1). The diagram of the op-amp is shown in Figure 2. The design was copied from a bulk design for the regular SO1 devices and adapted for the twin gate devices in such a way that the sum of the twin gate lengths are equal to the corresponding gate length in the amplifiers with regular SO1 devices (e.g., to a 6 pm device in the design with regular transistors corresponds a 4 pm + 2 pm twin-gate device in the twin-gate design). The twin-gate approach was used for n-channel devices only, since p-channel devices naturally have good output conductance. The design was not optimized for SOI. The experimental set-up for ac measurement is shown in Figure 3. A measured Bode diagram is presented in Figure 4. The low-frequency gain measured in the SO1 op-amps are up to 85 dB (regular SOI) and 88 dB (twin gate). A 60 dB figure had previously been measured in the case of bulk op-amps having the same design. The low-frequency gain is higher in the twin-gate devices, and the comer frequency is higher if the bias is large enough (> 33 pA) (not the case in Figure 4). A cut-off frequency (fT) of 3 MHz was obtained for a 30 pF load. Significantly higher fT values can be obtained if the op-amp drives integrated capacitors of smaller values (e.g. switched capacitors), since fT=g&&l~d. Spice implementation of an output conductance model is being carried out for accurate simulation of different amplifier design performances.

Switch Circuit and Method of Switching Radio Frequency Signals

Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

SoC Issues for RF Smart Dust

Abstract: Wireless sensor nodes are autonomous devices incorporating sensing, power, computation, and communication into one system. Applications for large scale networks of these nodes are presented in the context of their impact on the hardware design. The demand for low unit cost and multiyear lifetimes, combined with progress in CMOS and MEMS processing, are driving development of SoC solutions for sensor nodes at the cubic centimeter scale with a minimum number of off-chip components. Here, the feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication. Autonomous cubic millimeter nodes appear within reach, but process complexity and substantial sacrifices in performance involved with a true single-chip solution establish a tradeoff between integration and assembly.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

Abstract: The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.