B. Ginetti

Bio: B. Ginetti is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: CMOS & Differential nonlinearity. The author has an hindex of 3, co-authored 3 publications receiving 238 citations.

A CMOS 13-b cyclic RSD A/D converter

Abstract: A 13-b CMOS cyclic A/D converter that does not need trimming nor digital calibration is presented. The effects associated with the error on the gain factor 2 as well as the offset errors are corrected by taking full advantage of the redundant signed digit (RSD) principle. The gain error resulting from mismatches among switched capacitors is corrected by a novel strategy that implements an exact multiplication by four after two cycles. As a result, offset errors do not affect the integral or the differential linearities from the RSD algorithm. The remaining overall shift caused by offsets is reduced under the LSB level by a proper choice of capacitor switching sequence. The converter achieves 1/2 LSB integral and differential linearity at 25 kS/s; harmonic distortion is less than -83 dB. Chip area is 2.9 mm2 in a standard CMOS 3-mu-m technology, including control logic and the serial-to-parallel output shift register. Power consumption is 45 mW under +/-5-V supplies.

A 1.5 Ms/s 8-Bit Pipelined RSD A/D Converter

Abstract: An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than 1Lsb is presented. At clock frequency of 3Mhz, the circuit achieves a 1.5Msample/s data rate. Power consumption is 20mW and chip area is 2 mm2 in a 3??m CMOS technology.

A CMOS 13 bits Cyclic RSD A/D Converter

Abstract: A differential cyclic RSD A/D converter is presented where the capacitors mismatch error is corrected without extra clock-phase or added hardware. An offset error cancellation based on the RSD properties is also included. The ADC achieves 13 bits linearity at 25kS/s and dissipates 40mW. Die area is 2.25 sqmm in a 3?m CMOS process.

A digital background calibration technique for time-interleaved analog-to-digital converters

Abstract: A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.

CMOS Data Converters for Communications

Abstract: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

Comparator-based switched-capacitor circuits for scaled CMOS technologies

Abstract: A comparator-based switched-capacitor (CBSC) design method for sampled-data systems utilizes topologies similar to traditional opamp-based methods but relies on the detection of the virtual ground using a comparator instead of forcing it with feedback. A prototype 10b CBSC 1.5b/stage pipelined ADC is implemented in a 0.18mum CMOS process. The converter operates at 8MHz and consumes 2.5mW

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Abstract: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

Abstract: A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-/spl mu/m CMOS technology. The device occupies 15 mm/sup 2/ and dissipates 250 mW from a 5 V supply.