B. J. Mulvaney

Bio: B. J. Mulvaney is an academic researcher from Motorola. The author has contributed to research in topics: Harmonic balance & Krylov subspace. The author has an hindex of 4, co-authored 7 publications receiving 43 citations.

The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearity

Abstract: Krylov subspace techniques in harmonic balance simulations become increasingly ineffective when applied to strongly nonlinear circuits. This limitation is particularly important in the simulation if the circu it has components being operated in a very nonlinear region. Ev en if the circuit contains only a few very nonlinear components, Krylov methods using standard preconditioners can become ineffective. To overcome this problem, we present two adaptive preconditioners that dynamically exploit the properties of the harmonic balance Jacobian. With these techniques we have been able to retain the advantages of Krylov methods even for strongly nonlinear circuits. Some numerical experiments illustrating the techniques are presented.

New methods for speeding up computation of Newton updates in harmonic balance

Abstract: A new adaptive approach to solving large-dimension harmonic balance (HB) problems in RF circuit simulation is presented. The method is based on adjusting the order of the equation system according to the degree of nonlinearity of each node in the circuit. A block-diagonal preconditioner is used to construct an algorithm for order reduction during the iterative HB process.

Approximation Approach for Timing Jitter Characterization in Circuit Simulators

Abstract: A new computational concept of timing jitter is proposed that is suitable for exploitation in circuit simulators. It is based on the approximation of computed noise characteristics. To define jitter value the parameter representation is used. The desired parameters are obtained after noise simulation process in time domain by minimization of integral residual L/sub 2/-norm. The approach is illustrated by examples of jitter computation using spice-like simulator.

A new approach for computation of timing jitter in phase locked loops

Abstract: A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with modulated stationary noise models, spectral decomposition of stochastic process and decomposition of noise into orthogonal components i.e. phase and amplitude noise. The method is illustrated by examples of jitter computation in PLLs.

A Linear-Centric Modeling Approach to Harmonic Balance Analysis

Abstract: In this paper, we propose a new harmonic balance simulation methodology based on a linear-centric modeling approach. A linear circuit representation of the nonlinear devices and associated parasitics is used along with corresponding time and frequency domain inputs to solve for the nonlinear steady-state response via successive chord (SC) iterations. For our circuit examples, this approach is shown to be up to 60/spl times/ more run-time efficient than traditional Newton-Raphson (N-R) based iterative methods, while providing the same level of accuracy. This SC-based approach converges as reliably as the N-R approaches, including for circuit problems which cause alternative relaxation-based harmonic balance approaches to fail. The efficacy of this linear-centric methodology further improves with increasing model complexity, the inclusion of interconnect parasitics and other analyses that are otherwise difficult with traditional nonlinear models.

Fundamentals of Fast Simulation Algorithms for RF Circuits

Abstract: Designers of RF circuits such as power amplifiers, mixers, and filters make extensive use of simulation tools which perform periodic steady-state analysis and its extensions, but until the mid 1990s, the computational costs of these simulation tools restricted designers from simulating the behavior of complete RF subsystems. The introduction of fast matrix-implicit iterative algorithms completely changed this situation, and extensions of these fast methods are providing tools which can perform periodic, quasi-periodic, and periodic noise analysis of circuits with thousands of devices. Even though there are a number of research groups continuing to develop extensions of matrix-implicit methods, there is still no compact characterization which introduces the novice researcher to the fundamental issues. In this paper, we examine the basic periodic steady-state problem and provide both examples and linear algebra abstractions to demonstrate connections between seemingly dissimilar methods and to try to provide a more general framework for fast methods than the standard time-versus-frequency domain characterization of finite-difference, basis-collocation, and shooting methods

RF S-parameter degradation under hot carrier stress

Abstract: The increasing high frequency capabilities of CMOS have resulted in increased RF and analog design in CMOS. Design of RF and analog circuits depends critically on device S-parameter characteristics, magnitude of real and imaginary components and their behavior as a function of frequency. Utilization of scaled high performance CMOS technologies poses challenges as concerns for reliability degradation mechanisms increase. It is important to understand and quantify the effects of the reliability degradation mechanisms on the S-parameters and in turn on RF and analog applications. Current modeling of voltage stress effects normally is limited to low frequency parameters, as is in-line characterization. In this paper we discuss the relationship between the low frequency parameters commonly characterized & modeled with the shifts in RF properties of MOSFETs.

Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit Analysis

Abstract: As a widely adopted frequency-domain method, harmonic balance (HB) provides efficient steady-state circuit analysis for analog and RF circuits. The conventional matrix-implicit Krylov subspace technique with the block-diagonal (BD) preconditioner has made it possible to compute the steady-state responses of large-scale circuits. However, not all HB problems, particularly strongly nonlinear circuit problems, can be solved reliably or efficiently using the standard BD-preconditioning technique. In this paper, hierarchical HB methods are proposed wherein robust preconditioning is provided via solution of a set of approximate linearized HB problems of progressively smaller size across multiple levels of the problem hierarchy. These subproblems are constructed using the same matrix-implicit formulation to retain the memory efficiency of Krylov subspace methods. Moreover, the number of allocated Krylov subspace matrix solvers, hence the memory usage, is significantly reduced via a recently introduced solver-sharing technique. The efficiency of our hierarchical preconditioning technique is further improved by adopting a one-step correction to the standard BD preconditioner and a multigrid-motivated iterative scheme. It has been shown that the proposed approaches can achieve up to 10 runtime speedup over the popular BD preconditioner and robust convergence even for strongly nonlinear circuits for which the BD preconditioner fails to converge.