We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program are unwound and translated into a formula that represents behavioral consistency. The formula is then checked using a SAT solver. We are able to translate C programs that include side effects, pointers, dynamic memory allocation, and loops with conditions that cannot be evaluated statically. We describe experimental results on various reactive circuits and programs, including a small processor given in Verilog and its Instruction Set Architecture given in ANSI-C.

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Behavioral consistency of C and Verilog programs using bounded model checking

A method, apparatus and data construct set for generating simulation data structures which can be used by a modeling system to interface between a PLC and simulator, the construct set encapsulating logic and at least a sub-set of simulation information for a particular resource.

Simulation method and apparatus for use in enterprise controls

A method for identifying at least a section of a first schematic associated with at least a section of a second schematic wherein each of the first and second schematics includes a set of components for configuring a system to perform a process and wherein the components of the first and second schematics are first and second different types, respectively, the method comprising the steps of identifying the components of the first type included in the first section of the first schematic, examining the second schematic to identify at least one instance of components of the second type that are associated with the identified components of the first type and when at least one instance of components of the second type is identified, rendering the at least one instance accessible.

Mechanical-electrical template based method and apparatus

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Method and apparatus for managing the configuration and functionality of a semiconductor design

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

A system for specifying, synthesizing, analyzing, simulating, and generating circuit designs for frame protocols. A GUI allows a user to specify a frame protocol and to edit and browse frame protocols. The GUI also allows the user to analyze an intermediate virtual circuit resulting from the protocol and to check the syntax of the protocol specification. In addition, the GUI allows the user to generate a High-level Description Language (HDL) file for the protocol. After the HDL is generated, the user can, through the GUI, simulate the operation of the HDL. The present invention includes a "SIMPLUG" feature that specifies a standard interface for GUI software 110, allowing the GUI to operate with a variety of simulators. The present invention also "back annotates" the virtual circuit to provide information in the virtual circuit that is used during simulation to indicate information about individual frames in the protocol. The present invention also optimizes both the virtual circuit and intermediate state transition graphs in accordance with the level of optimization specified by the user.

System for frame-based protocol, graphical capture, synthesis, analysis, and simulation

This paper describes a system for designing and implementing controllers for structured data processing. A graphical input style describes the format of the data to be processed along with the necessary control actions. Advantages over FSM approaches include: (1) ease of design changes, (2) ease of debugging, and (3) a shorter design cycle.

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A system for compiling and debugging structured data processing controllers

A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

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B. Pangrle

Papers

System for frame-based protocol, graphical capture, synthesis, analysis, and simulation

A system for compiling and debugging structured data processing controllers

RTL C-based methodology for designing and verifying a multi-threaded processor