A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

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A 10-b 20-Msample/s analog-to-digital converter

The state of the art of continuous-time filter design is reviewed Several techniques are discussed and compared in terms of performance and implementation feasibility in different fabrication technologies This review does not aim at historical completeness, but rather emphasizes techniques that have proven their worth in commercial applications Brief mention is also made of experimental work which, in the opinion of the author, shows promise for the future >

Integrated continuous-time filter design /spl minus/ an overview

CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Kickback noise reduction techniques for CMOS latched comparators

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS

A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

Digital-domain calibration of multistep analog-to-digital converters

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1- mu m CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm/sup 2/ (2700 mil/sup 2/). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters. >

A 10-b 15-MHz CMOS recycling two-step A/D converter

A low-distortion MOSFET-C filter design is proposed. The proposed technique relies on the linearity of the passive resistors and the tunability of current-steering MOS transistors operating in the triode region. Placing the nonlinear elements inside the feedback loops and degenerating the MOSFETs by passive resistors, greatly reduces the distortion resulting from the nonlinear devices. A prototype 22-kHz Bessel filter automatically tuned to a switched-capacitor reference resistor has control voltage feedthrough below -100 dB, and measured linearity better than -90-dB THD (total harmonic distortion), with a 2-kHz, 4-V/sub pp/ voltage swing. Measured THD demonstrates an improvement of at least 30 dB over a conventional MOSFETC filter. The chip consumes 40 mW with a 5-V supply, and the active die area is 7 mm/sup 2/ in 2- mu m double-poly CMOS. >

http://ieeexplore.ieee.org/iel2/1057/6932/00280063.pdf

B.-S. Song

Papers

Digital-domain calibration of multistep analog-to-digital converters

A 10-b 15-MHz CMOS recycling two-step A/D converter

A low-distortion 22 kHz 5th-order Bessel filter