Balaji Narasimham

Bio: Balaji Narasimham is an academic researcher from Broadcom. The author has contributed to research in topics: Soft error & Single event upset. The author has an hindex of 17, co-authored 54 publications receiving 787 citations.

Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

Abstract: Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Impact of Technology Scaling on SRAM Soft Error Rates

Abstract: Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Abstract: Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or nearmore » normal incidence for the bulk circuits.« less

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

Abstract: A novel circuit design for separating single-event transients due to N-hits and P-hits is described. Measurement results obtained from a 65 nm technology using heavy-ions show different dominant mechanisms for charge collection for P-hits and N-hits. The data collected represent the first such separation of SET pulse widths for 65 nm bulk CMOS technology. For low LET particles, N-hit transients are longer, but for high LET particles, P-hit transients are longer. N-well depth and the parasitic bipolar effect are shown to be the most important parameters affecting transient pulse widths.

Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths

Abstract: Heavy-ion data from a 130-nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands, which are well contacts that surround individual transistors, can reduce single-event pulsewidths for normal strikes, but increase them for angled strikes. Calibrated 3-D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device.

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Single Event Transients in Digital CMOS—A Review

Abstract: The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

Methods for fault tolerance in networks-on-chip

Abstract: Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.