Benoit Bakeroot

Bio: Benoit Bakeroot is an academic researcher from Ghent University. The author has contributed to research in topics: Schottky diode & Leakage (electronics). The author has an hindex of 22, co-authored 90 publications receiving 1389 citations. Previous affiliations of Benoit Bakeroot include Katholieke Universiteit Leuven & IMEC.

Forward Bias Gate Breakdown Mechanism in Enhancement-Mode p-GaN Gate AlGaN/GaN High-Electron Mobility Transistors

Abstract: In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized We report for the first time on the observation of a positive temperature dependence, ie, a higher temperature leads to a higher gate breakdown voltage Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

Abstract: High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

Analysis of the Gate Capacitance–Voltage Characteristics in p-GaN/AlGaN/GaN Heterostructures

Abstract: In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the ${C}$ – ${V}$ behavior depends on the different processing conditions of the p-GaN gate. Second, a two-junction capacitor model considering a series connection of the Schottky metal/p-GaN junction capacitor and the AlGaN barrier capacitor is proposed to explain this ${C}$ – ${V}$ behavior. Based on this model, the junction capacitance has an influence on the total capacitance value under a high gate bias due to the Schottky metal/p-GaN junction. Furthermore, the Mg-concentration and hole density can be extracted. The extracted hole density is consistent with the results obtained by Hall measurements.

Analytical Model for the Threshold Voltage of ${p}$ -(Al)GaN High-Electron-Mobility Transistors

Abstract: An analytical model for the calculation of the threshold voltage for enhancement-mode (E-mode) ${p}$ -(Al)GaN high-electron-mobility transistors (HEMTs) is presented. The ON-state behavior (at low output voltages) of both ${p}$ -GaN HEMTs and ${p}$ -AlGaN HEMTs—including the gate injection transistor—are discussed in detail, and closed expressions for the threshold voltage ${V}_{T}$ of both devices are deduced. It is found that the threshold voltage values for both devices are close to one another, and that there is an ideal upper limit when the ${p}$ -type doping in the AlGaN gate is perfectly tailored, yielding more positive threshold voltages. This ideal case might be difficult to realize technologically, but can serve as a benchmark for the ${V}_{T}$ of ${p}$ -(Al)GaN HEMTs.

Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode With Gated Edge Termination on 200-mm Silicon Substrate

Abstract: In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of on -state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver $\sim 4$ A at 2 V and show a median leakage of 1.3 $\mu \text{A}$ at 25 °C and 3.8 $\mu \text{A}$ at 150 °C measured at a reverse voltage of −200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing ( $L_{\mathrm{ AC}}$ ) and the length of field plate. We observed a saturated BV of $\sim 600$ V for the GET-SBDs with $L_{\mathrm{ AC}}$ larger than 5 $\mu \text{m}$ . The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 $\mu \text{m}$ -thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension $L_{G}$ (from 2 to 0.75 $\mu \text{m}$ ) and remains at a value of $\sim 10$ nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.

GaN-on-Si Power Technology: Devices and Applications

Abstract: In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

The 2018 GaN power electronics roadmap

Abstract: Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Maximizing the Performance of 650-V p-GaN Gate HEMTs: Dynamic RON Characterization and Circuit Design Considerations

Abstract: The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic R ON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$ . While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic R ON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$ ; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices.