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Beom-Mo Han

Bio: Beom-Mo Han is an academic researcher from Qualcomm. The author has contributed to research in topics: Static random-access memory & Noise margin. The author has an hindex of 7, co-authored 12 publications receiving 142 citations.

Papers
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Patent
06 Nov 2008
TL;DR: In this article, a method of fabricating a semiconductor using a fin field effect transistor (FINFET) is described, which includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width.
Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

36 citations

Journal ArticleDOI
TL;DR: In this article, the design space, including fin thickness, fin height, fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints.
Abstract: In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

33 citations

Patent
04 Nov 2010
TL;DR: In this paper, the authors propose to adjust drive strengths of pull-up and pass-gate devices during read and write operations to improve RSNM and WNM by adjusting drive strengths during read-and write operations.
Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

16 citations

Patent
02 Sep 2009
TL;DR: In this article, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at the first BOX layer face.
Abstract: A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.

15 citations

Patent
25 Mar 2011
TL;DR: In this article, a 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation, which includes a storage element for storing data, wherein the storage element is coupled a first voltage and a ground voltage.
Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM (400) includes a storage element (402) for storing data, wherein the storage element is coupled a first voltage and a ground voltage. The storage element can include symmetrically sized cross - coupled inverters. A single access transistor (M5 ) controls read and write operations on the storage element (402). Control logic (M6,M6') is configured to generate a value of the first voltage for a write operation that is different from the value of the first voltage for a read operation.

14 citations


Cited by
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Patent
Jhon Jhy Liaw1, Jeng-Jung Shen1
30 Jun 2010
TL;DR: In this article, a static random access memory (SRAM) cell with a plurality of active regions formed on a semiconductor substrate is presented, where the active regions include a pair adjacent active regions having a first spacing and a fin active region having a second spacing from adjacent regions, the second spacing being greater than the first spacing.
Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

228 citations

Patent
Hong-bae Park1, Ja-hum Ku1, Myeong-cheol Kim1, Jin-Wook Lee1, Sung-Kee Han1 
19 Sep 2016
TL;DR: In this article, the authors proposed a method for providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of the active regions, where each of the first gate line and second gate line crossing at least one active region.
Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

211 citations

Journal ArticleDOI
TL;DR: Research on FinFETs from the bottommost device level to the topmost architecture level is reviewed and various possible FinFet asymmetries and their impact are surveyed, and novel logic-level and architecture-level tradeoffs offered by FinFetts are surveyed.
Abstract: Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

142 citations

Patent
05 Sep 2008
TL;DR: In this paper, the conductive structure is formed over at least part of the planar portion and not over the protrusion portion of the via structure of a semiconductor device.
Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

95 citations

Patent
Jhon Jhy Liaw1
27 Mar 2015
TL;DR: In this paper, an SRAM array and method of making is disclosed, which includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins.
Abstract: An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

84 citations