B
Bertrand Parvais
Researcher at Katholieke Universiteit Leuven
Publications - 179
Citations - 3051
Bertrand Parvais is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 28, co-authored 155 publications receiving 2461 citations. Previous affiliations of Bertrand Parvais include VU University Amsterdam & IMEC.
Papers
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Proceedings ArticleDOI
3D stacked IC demonstration using a through Silicon Via First approach
J. Van Olmen,Abdelkarim Mercha,G. Katti,Cedric Huyghebaert,J. Van Aelst,E. Seppala,Zhao Chao,Silvia Armini,Jan Vaes,R. C. Teixeira,M. Van Cauwenberghe,Patrick Verdonck,K. Verhemeldonck,Anne Jourdain,Wouter Ruythooren,M. de Potter de ten Broeck,A. Opdebeeck,Thomas Chiarella,Bertrand Parvais,Ingrid Debusschere,T. Y. Hoffmann,B. De Wachter,Wim Dehaene,Michele Stucchi,Michal Rakowski,Philippe Soussan,R. Cartuyvels,Eric Beyne,Serge Biesemans,Bart Swinnen +29 more
TL;DR: In this paper, the authors report the first demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV), which is inserted between contact and M1 of their reference 0.13 mum CMOS process on 200 mm wafers.
Journal ArticleDOI
Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective
V. Subramanian,Bertrand Parvais,Jonathan Borremans,Abdelkarim Mercha,D. Linten,P. Wambacq,Josine Loo,Morin Dehan,C. Gustin,Nadine Collaert,Stefan Kubicek,R.J.P. Lander,J. Hooker,F. N. Cubaynes,Stéphane Donnay,Malgorzata Jurczak,Guido Groeseneken,Willy Sansen,Stefaan Decoutere +18 more
TL;DR: In this paper, the authors compared the performance of FinFETs and planar bulk MOSFET and found that the latter has better voltage gain without degradation of noise or linearity.
Journal ArticleDOI
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Thomas Chiarella,Liesbeth Witters,Abdelkarim Mercha,Christoph Kerner,Michal Rakowski,C. Ortolland,Lars-Ake Ragnarsson,Bertrand Parvais,A. De Keersgieter,S. Kubicek,Augusto Redolfi,C. Vrancken,S. Brus,Anne Lauwers,Philippe Absil,Serge Biesemans,Thomas Hoffmann +16 more
TL;DR: In this paper, an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations is presented. And the authors demonstrate highperforming FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk Fin-FETs.
Proceedings ArticleDOI
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
Lars-Ake Ragnarsson,Zilan Li,J. Tseng,Tom Schram,E. Rohr,Moon Ju Cho,Thomas Kauerauf,Thierry Conard,Y. Okuno,Bertrand Parvais,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +12 more
TL;DR: In this article, a zero interface layer and optimized gate-electrode are used to achieve ultra low EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices.
Journal ArticleDOI
Fully-depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
Denis Flandre,Stéphane Adriaensen,A. Akheyar,André Crahay,Laurent Demeûs,P. Delatte,Vincent Dessard,Benjamin Iniguez,Amaury Nève,B Katschmarskyj,Pierre Loumaye,J. Laconte,I. Martinez,G. Picun,E. Rauly,Christian Renaux,D. Spôte,M Zitout,Morin Dehan,Bertrand Parvais,Pascal Simon,D. Vanhoenacker,Jean-Pierre Raskin +22 more
TL;DR: Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, the authors demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under lowvoltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC.